From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 16/36] exec.c: Use cpu_get_phys_page_attrs_debug
Date: Thu, 21 Jan 2016 14:56:09 +0000 [thread overview]
Message-ID: <1453388189-13092-17-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1453388189-13092-1-git-send-email-peter.maydell@linaro.org>
Use cpu_get_phys_page_attrs_debug() when doing virtual-to-physical
conversions in debug related code, so that we can obtain the right
address space index and thus select the correct AddressSpace,
rather than always using cpu->as.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
exec.c | 18 +++++++++++++-----
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/exec.c b/exec.c
index cbadca4..590a018 100644
--- a/exec.c
+++ b/exec.c
@@ -667,9 +667,11 @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
#else
static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
{
- hwaddr phys = cpu_get_phys_page_debug(cpu, pc);
+ MemTxAttrs attrs;
+ hwaddr phys = cpu_get_phys_page_attrs_debug(cpu, pc, &attrs);
+ int asidx = cpu_asidx_from_attrs(cpu, attrs);
if (phys != -1) {
- tb_invalidate_phys_addr(cpu->as,
+ tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
phys | (pc & ~TARGET_PAGE_MASK));
}
}
@@ -3586,8 +3588,12 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
target_ulong page;
while (len > 0) {
+ int asidx;
+ MemTxAttrs attrs;
+
page = addr & TARGET_PAGE_MASK;
- phys_addr = cpu_get_phys_page_debug(cpu, page);
+ phys_addr = cpu_get_phys_page_attrs_debug(cpu, page, &attrs);
+ asidx = cpu_asidx_from_attrs(cpu, attrs);
/* if no physical page mapped, return an error */
if (phys_addr == -1)
return -1;
@@ -3596,9 +3602,11 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
l = len;
phys_addr += (addr & ~TARGET_PAGE_MASK);
if (is_write) {
- cpu_physical_memory_write_rom(cpu->as, phys_addr, buf, l);
+ cpu_physical_memory_write_rom(cpu->cpu_ases[asidx].as,
+ phys_addr, buf, l);
} else {
- address_space_rw(cpu->as, phys_addr, MEMTXATTRS_UNSPECIFIED,
+ address_space_rw(cpu->cpu_ases[asidx].as, phys_addr,
+ MEMTXATTRS_UNSPECIFIED,
buf, l, 0);
}
len -= l;
--
1.9.1
next prev parent reply other threads:[~2016-01-21 14:56 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-21 14:55 [Qemu-devel] [PULL 00/36] target-arm queue Peter Maydell
2016-01-21 14:55 ` [Qemu-devel] [PULL 01/36] qdev: get_child_bus(): Use QOM lookup if available Peter Maydell
2016-01-21 14:55 ` [Qemu-devel] [PULL 02/36] m25p80.c: Add sst25wf080 SPI flash device Peter Maydell
2016-01-21 14:55 ` [Qemu-devel] [PULL 03/36] ssi: Move ssi.h into a separate directory Peter Maydell
2016-01-21 14:55 ` [Qemu-devel] [PULL 04/36] xilinx_spips: Separate the state struct into a header Peter Maydell
2016-01-21 14:55 ` [Qemu-devel] [PULL 05/36] xlnx-zynqmp: Connect the SPI devices Peter Maydell
2016-01-21 14:55 ` [Qemu-devel] [PULL 06/36] xlnx-ep108: Connect the SPI Flash Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 07/36] misc: zynq-xadc: Fix off-by-one Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 08/36] exec.c: Don't set cpu->as until cpu_address_space_init Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 09/36] exec.c: Allow target CPUs to define multiple AddressSpaces Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 10/36] exec-all.h: Document tlb_set_page_with_attrs, tlb_set_page Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 11/36] cpu: Add new get_phys_page_attrs_debug() method Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 12/36] cpu: Add new asidx_from_attrs() method Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 13/36] cputlb.c: Use correct address space when looking up MemoryRegionSection Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 14/36] exec.c: Pass MemTxAttrs to iotlb_to_region so it uses the right AS Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 15/36] exec.c: Add cpu_get_address_space() Peter Maydell
2016-01-21 14:56 ` Peter Maydell [this message]
2016-01-21 14:56 ` [Qemu-devel] [PULL 17/36] exec.c: Use correct AddressSpace in watch_mem_read and watch_mem_write Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 18/36] memory: Add address_space_init_shareable() Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 19/36] qom/cpu: Add MemoryRegion property Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 20/36] target-arm: Add QOM property for Secure memory region Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 21/36] target-arm: Implement asidx_from_attrs Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 22/36] target-arm: Implement cpu_get_phys_page_attrs_debug Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 23/36] target-arm: Support multiple address spaces in page table walks Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 24/36] hw/arm/virt: Wire up memory region to CPUs explicitly Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 25/36] hw/arm/virt: add secure memory region and UART Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 26/36] hw/arm/virt: Add always-on property to the virt board timer Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 27/36] arm_gic: Update ID registers based on revision Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 28/36] target-arm: Properly support EL2 and EL3 in arm_el_is_aa64() Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 29/36] target-arm: Move aarch64_cpu_do_interrupt() to helper.c Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 30/36] target-arm: Use a single entry point for AArch64 and AArch32 exceptions Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 31/36] target-arm: Pull semihosting handling out to arm_cpu_do_interrupt() Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 32/36] target-arm: Fix wrong AArch64 entry offset for EL2/EL3 target Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 33/36] target-arm: Handle exception return from AArch64 to non-EL0 AArch32 Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 34/36] target-arm: Implement remaining illegal return event checks Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 35/36] target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM mode Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 36/36] target-arm: Implement FPEXC32_EL2 system register Peter Maydell
2016-01-21 15:53 ` [Qemu-devel] [PULL 00/36] target-arm queue Peter Maydell
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