From: Leon Alrae <leon.alrae@imgtec.com>
To: qemu-devel@nongnu.org
Cc: Dongxue Zhang <elta.era@gmail.com>
Subject: [Qemu-devel] [PULL 1/4] target-mips/cpu.h: Fix spell error
Date: Mon, 25 Jan 2016 10:02:32 +0000 [thread overview]
Message-ID: <1453716155-9492-2-git-send-email-leon.alrae@imgtec.com> (raw)
In-Reply-To: <1453716155-9492-1-git-send-email-leon.alrae@imgtec.com>
From: Dongxue Zhang <elta.era@gmail.com>
CP0IntCtl_IPPC1, the last letter should be 'i', not 'one'.
Signed-off-by: Dongxue Zhang <elta.era@gmail.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
target-mips/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 89c01f7..17817c3 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -358,7 +358,7 @@ struct CPUMIPSState {
#define CP0St_IE 0
int32_t CP0_IntCtl;
#define CP0IntCtl_IPTI 29
-#define CP0IntCtl_IPPC1 26
+#define CP0IntCtl_IPPCI 26
#define CP0IntCtl_VS 5
int32_t CP0_SRSCtl;
#define CP0SRSCtl_HSS 26
--
2.1.0
next prev parent reply other threads:[~2016-01-25 10:03 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-25 10:02 [Qemu-devel] [PULL 0/4] target-mips queue Leon Alrae
2016-01-25 10:02 ` Leon Alrae [this message]
2016-01-25 10:02 ` [Qemu-devel] [PULL 2/4] target-mips: silence NaNs for cvt.s.d and cvt.d.s Leon Alrae
2016-01-25 10:02 ` [Qemu-devel] [PULL 3/4] target-mips: Fix ALIGN instruction when bp=0 Leon Alrae
2016-01-25 10:02 ` [Qemu-devel] [PULL 4/4] mips: Clean up includes Leon Alrae
2016-01-25 11:31 ` [Qemu-devel] [PULL 0/4] target-mips queue Peter Maydell
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