From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53461) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aOe4u-00020v-Pa for qemu-devel@nongnu.org; Wed, 27 Jan 2016 23:21:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aOe4t-00053Z-OQ for qemu-devel@nongnu.org; Wed, 27 Jan 2016 23:21:04 -0500 Message-ID: <1453954855.3148.52.camel@kernel.crashing.org> From: Benjamin Herrenschmidt Date: Thu, 28 Jan 2016 15:20:55 +1100 In-Reply-To: <1453889591-30968-8-git-send-email-david@gibson.dropbear.id.au> References: <1453889591-30968-1-git-send-email-david@gibson.dropbear.id.au> <1453889591-30968-8-git-send-email-david@gibson.dropbear.id.au> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCHv2 07/10] target-ppc: Split 44x tlbiva from ppc_tlb_invalidate_one() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson Cc: lvivier@redhat.com, thuth@redhat.com, aik@ozlabs.ru, agraf@suse.de, qemu-devel@nongnu.org, qemu-ppc@nongnu.org On Wed, 2016-01-27 at 21:13 +1100, David Gibson wrote: > Currently both the tlbiva instruction (used on 44x chips) and the > tlbie > instruction (used on hash MMU chips) are both handled via > ppc_tlb_invalidate_one().=C2=A0=C2=A0This is silly, because they're inv= oked > from > different places, and do different things. >=20 > Clean this up by separating out the tlbiva instruction into its own > handling.=C2=A0=C2=A0In fact the implementation is only a stub anyway. >=20 > Signed-off-by: David Gibson Acked-by: Benjamin Herrenschmidt > --- > =C2=A0target-ppc/helper.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0|=C2=A0=C2=A01 + > =C2=A0target-ppc/mmu_helper.c | 14 ++++++++++---- > =C2=A0target-ppc/translate.c=C2=A0=C2=A0|=C2=A0=C2=A02 +- > =C2=A03 files changed, 12 insertions(+), 5 deletions(-) >=20 > diff --git a/target-ppc/helper.h b/target-ppc/helper.h > index 869be15..e5a8f7b 100644 > --- a/target-ppc/helper.h > +++ b/target-ppc/helper.h > @@ -544,6 +544,7 @@ DEF_HELPER_2(74xx_tlbd, void, env, tl) > =C2=A0DEF_HELPER_2(74xx_tlbi, void, env, tl) > =C2=A0DEF_HELPER_FLAGS_1(tlbia, TCG_CALL_NO_RWG, void, env) > =C2=A0DEF_HELPER_FLAGS_2(tlbie, TCG_CALL_NO_RWG, void, env, tl) > +DEF_HELPER_FLAGS_2(tlbiva, TCG_CALL_NO_RWG, void, env, tl) > =C2=A0#if defined(TARGET_PPC64) > =C2=A0DEF_HELPER_FLAGS_3(store_slb, TCG_CALL_NO_RWG, void, env, tl, tl) > =C2=A0DEF_HELPER_2(load_slb_esid, tl, env, tl) > diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c > index 82ebe5d..e9e0edb 100644 > --- a/target-ppc/mmu_helper.c > +++ b/target-ppc/mmu_helper.c > @@ -1971,10 +1971,6 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, > target_ulong addr) > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0ppc6xx_tlb_invalidate_virt(env, addr, 1); > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0break; > -=C2=A0=C2=A0=C2=A0=C2=A0case POWERPC_MMU_BOOKE: > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0/* XXX: TODO */ > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0cpu_abort(CPU(cpu), "B= ookE MMU model is not implemented\n"); > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0break; > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0case POWERPC_MMU_32B: > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0case POWERPC_MMU_601: > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0/* tlbie invalida= te TLBs for all segments */ > @@ -2116,6 +2112,16 @@ void helper_tlbie(CPUPPCState *env, > target_ulong addr) > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0ppc_tlb_invalidate_one(env, addr); > =C2=A0} > =C2=A0 > +void helper_tlbiva(CPUPPCState *env, target_ulong addr) > +{ > +=C2=A0=C2=A0=C2=A0=C2=A0PowerPCCPU *cpu =3D ppc_env_get_cpu(env); > + > +=C2=A0=C2=A0=C2=A0=C2=A0/* tlbiva instruciton only exists on BookE */ > +=C2=A0=C2=A0=C2=A0=C2=A0assert(env->mmu_model =3D=3D POWERPC_MMU_BOOKE= ); > +=C2=A0=C2=A0=C2=A0=C2=A0/* XXX: TODO */ > +=C2=A0=C2=A0=C2=A0=C2=A0cpu_abort(CPU(cpu), "BookE MMU model is not im= plemented\n"); > +} > + > =C2=A0/* Software driven TLBs management */ > =C2=A0/* PowerPC 602/603 software TLB load instructions helpers */ > =C2=A0static void do_6xx_tlb(CPUPPCState *env, target_ulong new_EPN, in= t > is_code) > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index 4be7eaa..a05a169 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -5904,7 +5904,7 @@ static void gen_tlbiva(DisasContext *ctx) > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0t0 =3D tcg_temp_new(); > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0gen_addr_reg_index(ctx, t0); > -=C2=A0=C2=A0=C2=A0=C2=A0gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opco= de)]); > +=C2=A0=C2=A0=C2=A0=C2=A0gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opc= ode)]); > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0tcg_temp_free(t0); > =C2=A0#endif > =C2=A0}