From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50629) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aOfUA-00029Z-Ut for qemu-devel@nongnu.org; Thu, 28 Jan 2016 00:51:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aOfU7-0005CS-Fv for qemu-devel@nongnu.org; Thu, 28 Jan 2016 00:51:14 -0500 Received: from e23smtp08.au.ibm.com ([202.81.31.141]:38839) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aOfU6-0005BK-F6 for qemu-devel@nongnu.org; Thu, 28 Jan 2016 00:51:11 -0500 Received: from localhost by e23smtp08.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 28 Jan 2016 15:51:08 +1000 From: Bharata B Rao Date: Thu, 28 Jan 2016 11:19:46 +0530 Message-Id: <1453960195-15181-5-git-send-email-bharata@linux.vnet.ibm.com> In-Reply-To: <1453960195-15181-1-git-send-email-bharata@linux.vnet.ibm.com> References: <1453960195-15181-1-git-send-email-bharata@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH v7 04/13] cpu: Don't realize CPU from cpu_generic_init() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: mjrosato@linux.vnet.ibm.com, ehabkost@redhat.com, aik@ozlabs.ru, Bharata B Rao , mdroth@linux.vnet.ibm.com, agraf@suse.de, pbonzini@redhat.com, qemu-ppc@nongnu.org, tyreld@linux.vnet.ibm.com, nfont@linux.vnet.ibm.com, imammedo@redhat.com, afaerber@suse.de, david@gibson.dropbear.id.au Don't do CPU realization from cpu_generic_init(). With this cpu_generic_init() will be used to just create CPU threads and they should be realized separately from realizefn call. Convert the existing callers to do explicit realization. Signed-off-by: Bharata B Rao Reviewed-by: David Gibson Reviewed-by: Eduardo Habkost --- qom/cpu.c | 6 ------ target-arm/helper.c | 16 +++++++++++++++- target-cris/cpu.c | 16 +++++++++++++++- target-lm32/helper.c | 16 +++++++++++++++- target-moxie/cpu.c | 16 +++++++++++++++- target-openrisc/cpu.c | 16 +++++++++++++++- target-ppc/translate_init.c | 16 +++++++++++++++- target-sh4/cpu.c | 16 +++++++++++++++- target-tricore/helper.c | 16 +++++++++++++++- target-unicore32/helper.c | 16 +++++++++++++++- 10 files changed, 135 insertions(+), 15 deletions(-) diff --git a/qom/cpu.c b/qom/cpu.c index 8f537a4..01fd776 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -63,13 +63,7 @@ CPUState *cpu_generic_init(const char *typename, const char *cpu_model) featurestr = strtok(NULL, ","); cc->parse_features(cpu, featurestr, &err); g_free(str); - if (err != NULL) { - goto out; - } - - object_property_set_bool(OBJECT(cpu), true, "realized", &err); -out: if (err != NULL) { error_report_err(err); object_unref(OBJECT(cpu)); diff --git a/target-arm/helper.c b/target-arm/helper.c index ae02486..4a46cdb 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -4564,7 +4564,21 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPU *cpu_arm_init(const char *cpu_model) { - return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model)); + CPUState *cpu = cpu_generic_init(TYPE_ARM_CPU, cpu_model); + Error *err = NULL; + + if (!cpu) { + return NULL; + } + + object_property_set_bool(OBJECT(cpu), true, "realized", &err); + if (err != NULL) { + error_report_err(err); + object_unref(OBJECT(cpu)); + return NULL; + } else { + return ARM_CPU(cpu); + } } void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) diff --git a/target-cris/cpu.c b/target-cris/cpu.c index 8eaf5a5..d2c0822 100644 --- a/target-cris/cpu.c +++ b/target-cris/cpu.c @@ -89,7 +89,21 @@ static ObjectClass *cris_cpu_class_by_name(const char *cpu_model) CRISCPU *cpu_cris_init(const char *cpu_model) { - return CRIS_CPU(cpu_generic_init(TYPE_CRIS_CPU, cpu_model)); + CPUState *cpu = cpu_generic_init(TYPE_CRIS_CPU, cpu_model); + Error *err = NULL; + + if (!cpu) { + return NULL; + } + + object_property_set_bool(OBJECT(cpu), true, "realized", &err); + if (err != NULL) { + error_report_err(err); + object_unref(OBJECT(cpu)); + return NULL; + } else { + return CRIS_CPU(cpu); + } } /* Sort alphabetically by VR. */ diff --git a/target-lm32/helper.c b/target-lm32/helper.c index e26c133..49ac960 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -218,7 +218,21 @@ bool lm32_cpu_exec_interrupt(CPUState *cs, int interrupt_request) LM32CPU *cpu_lm32_init(const char *cpu_model) { - return LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model)); + CPUState *cpu = cpu_generic_init(TYPE_LM32_CPU, cpu_model); + Error *err = NULL; + + if (!cpu) { + return NULL; + } + + object_property_set_bool(OBJECT(cpu), true, "realized", &err); + if (err != NULL) { + error_report_err(err); + object_unref(OBJECT(cpu)); + return NULL; + } else { + return LM32_CPU(cpu); + } } /* Some soc ignores the MSB on the address bus. Thus creating a shadow memory diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c index 0c60c65..5989fa6 100644 --- a/target-moxie/cpu.c +++ b/target-moxie/cpu.c @@ -152,7 +152,21 @@ static const MoxieCPUInfo moxie_cpus[] = { MoxieCPU *cpu_moxie_init(const char *cpu_model) { - return MOXIE_CPU(cpu_generic_init(TYPE_MOXIE_CPU, cpu_model)); + CPUState *cpu = cpu_generic_init(TYPE_MOXIE_CPU, cpu_model); + Error *err = NULL; + + if (!cpu) { + return NULL; + } + + object_property_set_bool(OBJECT(cpu), true, "realized", &err); + if (err != NULL) { + error_report_err(err); + object_unref(OBJECT(cpu)); + return NULL; + } else { + return MOXIE_CPU(cpu); + } } static void cpu_register(const MoxieCPUInfo *info) diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index cc5e2d1..873eafb 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -222,7 +222,21 @@ static void openrisc_cpu_register_types(void) OpenRISCCPU *cpu_openrisc_init(const char *cpu_model) { - return OPENRISC_CPU(cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model)); + CPUState *cpu = cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model); + Error *err = NULL; + + if (!cpu) { + return NULL; + } + + object_property_set_bool(OBJECT(cpu), true, "realized", &err); + if (err != NULL) { + error_report_err(err); + object_unref(OBJECT(cpu)); + return NULL; + } else { + return OPENRISC_CPU(cpu); + } } /* Sort alphabetically by type name, except for "any". */ diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index f6babd2..3304ad1 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -9428,7 +9428,21 @@ static ObjectClass *ppc_cpu_class_by_name(const char *name) PowerPCCPU *cpu_ppc_init(const char *cpu_model) { - return POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model)); + CPUState *cpu = cpu_generic_init(TYPE_POWERPC_CPU, cpu_model); + Error *err = NULL; + + if (!cpu) { + return NULL; + } + + object_property_set_bool(OBJECT(cpu), true, "realized", &err); + if (err != NULL) { + error_report_err(err); + object_unref(OBJECT(cpu)); + return NULL; + } else { + return POWERPC_CPU(cpu); + } } /* Sort by PVR, ordering special case "host" last. */ diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c index d7e2fbd..e5151a0 100644 --- a/target-sh4/cpu.c +++ b/target-sh4/cpu.c @@ -155,7 +155,21 @@ static ObjectClass *superh_cpu_class_by_name(const char *cpu_model) SuperHCPU *cpu_sh4_init(const char *cpu_model) { - return SUPERH_CPU(cpu_generic_init(TYPE_SUPERH_CPU, cpu_model)); + CPUState *cpu = cpu_generic_init(TYPE_SUPERH_CPU, cpu_model); + Error *err = NULL; + + if (!cpu) { + return NULL; + } + + object_property_set_bool(OBJECT(cpu), true, "realized", &err); + if (err != NULL) { + error_report_err(err); + object_unref(OBJECT(cpu)); + return NULL; + } else { + return SUPERH_CPU(cpu); + } } static void sh7750r_cpu_initfn(Object *obj) diff --git a/target-tricore/helper.c b/target-tricore/helper.c index 1b70429..bf164fc 100644 --- a/target-tricore/helper.c +++ b/target-tricore/helper.c @@ -83,7 +83,21 @@ int cpu_tricore_handle_mmu_fault(CPUState *cs, target_ulong address, TriCoreCPU *cpu_tricore_init(const char *cpu_model) { - return TRICORE_CPU(cpu_generic_init(TYPE_TRICORE_CPU, cpu_model)); + CPUState *cpu = cpu_generic_init(TYPE_TRICORE_CPU, cpu_model); + Error *err = NULL; + + if (!cpu) { + return NULL; + } + + object_property_set_bool(OBJECT(cpu), true, "realized", &err); + if (err != NULL) { + error_report_err(err); + object_unref(OBJECT(cpu)); + return NULL; + } else { + return TRICORE_CPU(cpu); + } } static void tricore_cpu_list_entry(gpointer data, gpointer user_data) diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c index ae63277..e47bb12 100644 --- a/target-unicore32/helper.c +++ b/target-unicore32/helper.c @@ -27,7 +27,21 @@ UniCore32CPU *uc32_cpu_init(const char *cpu_model) { - return UNICORE32_CPU(cpu_generic_init(TYPE_UNICORE32_CPU, cpu_model)); + CPUState *cpu = cpu_generic_init(TYPE_UNICORE32_CPU, cpu_model); + Error *err = NULL; + + if (!cpu) { + return NULL; + } + + object_property_set_bool(OBJECT(cpu), true, "realized", &err); + if (err != NULL) { + error_report_err(err); + object_unref(OBJECT(cpu)); + return NULL; + } else { + return UNICORE32_CPU(cpu); + } } uint32_t HELPER(clo)(uint32_t x) -- 2.1.0