[Qemu-devel] [PATCH 2/9] hw/mips: add ITC Storage Cells

[Leon Alrae <leon.alrae@imgtec.com>]

Define single structure for FIFO and Semaphore cells. Read-only FIFO bit
in the ITC cell tag indicates the type of the cell. If the ITC Storage
contains both types of cells then FIFOs are located before Semaphores.

Since issuing thread can get blocked on the access to a cell (in E/F
Synchronized and P/V Synchronized Views) each cell contains a bitmap
to track which threads are currently blocked.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 hw/misc/mips_itu.c         | 17 +++++++++++++++++
 include/hw/misc/mips_itu.h | 25 +++++++++++++++++++++++++
 2 files changed, 42 insertions(+)

diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c
index cf79bc6..d6f6905 100644
--- a/hw/misc/mips_itu.c
+++ b/hw/misc/mips_itu.c
@@ -116,6 +116,20 @@ static const MemoryRegionOps itc_storage_ops = {
     .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
+static void itc_reset_cells(MIPSITUState *s)
+{
+    int i;
+    int num_cell = get_num_cells(s);
+
+    memset(s->cell, 0, num_cell * sizeof(s->cell[0]));
+
+    for (i = 0; i < s->num_fifo; i++) {
+        s->cell[i].tag.E = 1;
+        s->cell[i].tag.FIFO = 1;
+        s->cell[i].tag.FIFODepth = ITC_CELL_DEPTH_SHIFT;
+    }
+}
+
 static void mips_itu_init(Object *obj)
 {
     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
@@ -151,6 +165,9 @@ static void mips_itu_realize(DeviceState *dev, Error **errp)
         ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) |
         (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS);
 
+    s->cell = g_new(ITCStorageCell, get_num_cells(s));
+    itc_reset_cells(s);
+
     memory_region_set_enabled(&s->storage_io, false);
 }
 
diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h
index 9ddd8b4..b3a4532 100644
--- a/include/hw/misc/mips_itu.h
+++ b/include/hw/misc/mips_itu.h
@@ -23,6 +23,30 @@
 #define TYPE_MIPS_ITU "mips-itu"
 #define MIPS_ITU(obj) OBJECT_CHECK(MIPSITUState, (obj), TYPE_MIPS_ITU)
 
+#define ITC_CELL_DEPTH_SHIFT 2
+#define ITC_CELL_DEPTH (1u << ITC_CELL_DEPTH_SHIFT)
+
+typedef struct ITCStorageCell {
+    struct {
+        uint8_t FIFODepth; /* Log2 of the cell depth */
+        uint8_t FIFOPtr; /* Number of elements in a FIFO cell */
+        uint8_t FIFO; /* 1 - FIFO cell, 0 - Semaphore cell */
+        uint8_t T; /* Trap Bit */
+        uint8_t F; /* Full Bit */
+        uint8_t E; /* Empty Bit */
+    } tag;
+
+    /* Index of the oldest element in the queue */
+    uint8_t fifo_out;
+
+    /* Circular buffer for FIFO. Semaphore cells use index 0 only */
+    uint64_t data[ITC_CELL_DEPTH];
+
+    /* Bitmap tracking blocked threads on the cell.
+       TODO: support >64 threads ? */
+    uint64_t blocked_threads;
+} ITCStorageCell;
+
 #define ITC_ADDRESSMAP_NUM 2
 
 typedef struct MIPSITUState {
@@ -34,6 +58,7 @@ typedef struct MIPSITUState {
     int32_t num_semaphores;
 
     /* ITC Storage */
+    ITCStorageCell *cell;
     MemoryRegion storage_io;
 
     /* ITC Configuration Tags */
-- 
2.1.0