From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38023) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aR2eK-0003rE-Vy for qemu-devel@nongnu.org; Wed, 03 Feb 2016 13:59:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aR2eK-0001AI-3e for qemu-devel@nongnu.org; Wed, 03 Feb 2016 13:59:32 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:57190) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aR2eJ-00018I-Mr for qemu-devel@nongnu.org; Wed, 03 Feb 2016 13:59:31 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.84) (envelope-from ) id 1aR2e9-0003ED-1V for qemu-devel@nongnu.org; Wed, 03 Feb 2016 18:59:21 +0000 From: Peter Maydell Date: Wed, 3 Feb 2016 18:59:12 +0000 Message-Id: <1454525960-12335-10-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1454525960-12335-1-git-send-email-peter.maydell@linaro.org> References: <1454525960-12335-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 09/17] target-arm: Don't report presence of EL2 if it doesn't exist List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org We already modify the processor feature bits to not report EL3 support to the guest if EL3 isn't enabled for the CPU we're emulating. Add similar support for not reporting EL2 unless it is enabled. This is necessary because real world guest code running at EL3 (trusted firmware or bootloaders) will query the ID registers to determine whether it should start a guest Linux kernel in EL2 or EL3. Signed-off-by: Peter Maydell Reviewed-by: Sergey Fedorov Message-id: 1454437242-10262-1-git-send-email-peter.maydell@linaro.org --- target-arm/cpu.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 0e582c4..7ddbf3d 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -650,6 +650,15 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) cpu->id_aa64pfr0 &= ~0xf000; } + if (!arm_feature(env, ARM_FEATURE_EL2)) { + /* Disable the hypervisor feature bits in the processor feature + * registers if we don't have EL2. These are id_pfr1[15:12] and + * id_aa64pfr0_el1[11:8]. + */ + cpu->id_aa64pfr0 &= ~0xf00; + cpu->id_pfr1 &= ~0xf000; + } + if (!cpu->has_mpu) { unset_feature(env, ARM_FEATURE_MPU); } -- 1.9.1