From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38091) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aR2eM-0003tj-Gh for qemu-devel@nongnu.org; Wed, 03 Feb 2016 13:59:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aR2eL-0001B8-AC for qemu-devel@nongnu.org; Wed, 03 Feb 2016 13:59:34 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:57190) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aR2eL-00018I-2v for qemu-devel@nongnu.org; Wed, 03 Feb 2016 13:59:33 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.84) (envelope-from ) id 1aR2e8-0003Dt-PX for qemu-devel@nongnu.org; Wed, 03 Feb 2016 18:59:20 +0000 From: Peter Maydell Date: Wed, 3 Feb 2016 18:59:08 +0000 Message-Id: <1454525960-12335-6-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1454525960-12335-1-git-send-email-peter.maydell@linaro.org> References: <1454525960-12335-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 05/17] target-arm: Rename check_s2_startlevel to check_s2_mmu_setup List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: "Edgar E. Iglesias" Rename check_s2_startlevel to check_s2_mmu_setup in preparation for additional checks. Signed-off-by: Edgar E. Iglesias Reviewed-by: Alex Bennée Message-id: 1453932970-14576-3-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- target-arm/helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index f5e6fb1..31ff650 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -6763,17 +6763,18 @@ typedef enum { } MMUFaultType; /* - * check_s2_startlevel + * check_s2_mmu_setup * @cpu: ARMCPU * @is_aa64: True if the translation regime is in AArch64 state * @startlevel: Suggested starting level * @inputsize: Bitsize of IPAs * @stride: Page-table stride (See the ARM ARM) * - * Returns true if the suggested starting level is OK and false otherwise. + * Returns true if the suggested S2 translation parameters are OK and + * false otherwise. */ -static bool check_s2_startlevel(ARMCPU *cpu, bool is_aa64, int level, - int inputsize, int stride) +static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, + int inputsize, int stride) { const int grainsize = stride + 3; int startsizecheck; @@ -7013,8 +7014,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, } /* Check that the starting level is valid. */ - ok = check_s2_startlevel(cpu, va_size == 64, level, - inputsize, stride); + ok = check_s2_mmu_setup(cpu, va_size == 64, level, inputsize, stride); if (!ok) { /* AArch64 reports these as level 0 faults. * AArch32 reports these as level 1 faults. -- 1.9.1