From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35544) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aR46U-0006fX-Im for qemu-devel@nongnu.org; Wed, 03 Feb 2016 15:32:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aR46T-0005ck-7N for qemu-devel@nongnu.org; Wed, 03 Feb 2016 15:32:42 -0500 Received: from mx1.redhat.com ([209.132.183.28]:36122) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aR46S-0005cc-WB for qemu-devel@nongnu.org; Wed, 03 Feb 2016 15:32:41 -0500 From: John Snow Date: Wed, 3 Feb 2016 15:32:22 -0500 Message-Id: <1454531555-32022-8-git-send-email-jsnow@redhat.com> In-Reply-To: <1454531555-32022-1-git-send-email-jsnow@redhat.com> References: <1454531555-32022-1-git-send-email-jsnow@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 07/20] i8257: make the DMA running method per controller List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, jsnow@redhat.com, =?UTF-8?q?Herv=C3=A9=20Poussineau?= From: Herv=C3=A9 Poussineau This removes some static/global variables, and we're now running only the required controller (master or slave) Signed-off-by: Herv=C3=A9 Poussineau Message-id: 1453843944-26833-7-git-send-email-hpoussin@reactos.org Signed-off-by: John Snow --- hw/dma/i8257.c | 75 ++++++++++++++++++++++++++--------------------------= ------ 1 file changed, 34 insertions(+), 41 deletions(-) diff --git a/hw/dma/i8257.c b/hw/dma/i8257.c index e4262be..e577ed4 100644 --- a/hw/dma/i8257.c +++ b/hw/dma/i8257.c @@ -62,6 +62,10 @@ typedef struct I8257State { I8257Regs regs[4]; MemoryRegion channel_io; MemoryRegion cont_io; + + QEMUBH *dma_bh; + bool dma_bh_scheduled; + int running; } I8257State; =20 static I8257State dma_controllers[2]; @@ -81,7 +85,7 @@ enum { =20 }; =20 -static void i8257_dma_run(void); +static void i8257_dma_run(void *opaque); =20 static int channels[8] =3D {-1, 2, 3, 1, -1, -1, -1, 0}; =20 @@ -221,7 +225,7 @@ static void i8257_write_cont(void *opaque, hwaddr npo= rt, uint64_t data, d->status &=3D ~(1 << (ichan + 4)); } d->status &=3D ~(1 << ichan); - i8257_dma_run(); + i8257_dma_run(d); break; =20 case 0x02: /* single mask */ @@ -229,7 +233,7 @@ static void i8257_write_cont(void *opaque, hwaddr npo= rt, uint64_t data, d->mask |=3D 1 << (data & 3); else d->mask &=3D ~(1 << (data & 3)); - i8257_dma_run(); + i8257_dma_run(d); break; =20 case 0x03: /* mode */ @@ -264,12 +268,12 @@ static void i8257_write_cont(void *opaque, hwaddr n= port, uint64_t data, =20 case 0x06: /* clear mask for all channels */ d->mask =3D 0; - i8257_dma_run(); + i8257_dma_run(d); break; =20 case 0x07: /* write mask for all channels */ d->mask =3D data; - i8257_dma_run(); + i8257_dma_run(d); break; =20 default: @@ -321,7 +325,7 @@ void DMA_hold_DREQ (int nchan) ichan =3D nchan & 3; linfo ("held cont=3D%d chan=3D%d\n", ncont, ichan); dma_controllers[ncont].status |=3D 1 << (ichan + 4); - i8257_dma_run(); + i8257_dma_run(&dma_controllers[ncont]); } =20 void DMA_release_DREQ (int nchan) @@ -332,13 +336,14 @@ void DMA_release_DREQ (int nchan) ichan =3D nchan & 3; linfo ("released cont=3D%d chan=3D%d\n", ncont, ichan); dma_controllers[ncont].status &=3D ~(1 << (ichan + 4)); - i8257_dma_run(); + i8257_dma_run(&dma_controllers[ncont]); } =20 -static void i8257_channel_run(int ncont, int ichan) +static void i8257_channel_run(I8257State *d, int ichan) { + int ncont =3D d->dshift; int n; - I8257Regs *r =3D &dma_controllers[ncont].regs[ichan]; + I8257Regs *r =3D &d->regs[ichan]; #ifdef DEBUG_DMA int dir, opmode; =20 @@ -359,52 +364,38 @@ static void i8257_channel_run(int ncont, int ichan) ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont); } =20 -static QEMUBH *dma_bh; -static bool dma_bh_scheduled; - -static void i8257_dma_run(void) +static void i8257_dma_run(void *opaque) { - I8257State *d; - int icont, ichan; + I8257State *d =3D opaque; + int ichan; int rearm =3D 0; - static int running =3D 0; =20 - if (running) { + if (d->running) { rearm =3D 1; goto out; } else { - running =3D 1; + d->running =3D 1; } =20 - d =3D dma_controllers; + for (ichan =3D 0; ichan < 4; ichan++) { + int mask; =20 - for (icont =3D 0; icont < 2; icont++, d++) { - for (ichan =3D 0; ichan < 4; ichan++) { - int mask; + mask =3D 1 << ichan; =20 - mask =3D 1 << ichan; - - if ((0 =3D=3D (d->mask & mask)) && (0 !=3D (d->status & (mas= k << 4)))) { - i8257_channel_run(icont, ichan); - rearm =3D 1; - } + if ((0 =3D=3D (d->mask & mask)) && (0 !=3D (d->status & (mask <<= 4)))) { + i8257_channel_run(d, ichan); + rearm =3D 1; } } =20 - running =3D 0; + d->running =3D 0; out: if (rearm) { - qemu_bh_schedule_idle(dma_bh); - dma_bh_scheduled =3D true; + qemu_bh_schedule_idle(d->dma_bh); + d->dma_bh_scheduled =3D true; } } =20 -static void i8257_dma_run_bh(void *unused) -{ - dma_bh_scheduled =3D false; - i8257_dma_run(); -} - void DMA_register_channel (int nchan, DMA_transfer_handler transfer_handler, void *opaque) @@ -469,7 +460,8 @@ int DMA_write_memory (int nchan, void *buf, int pos, = int len) */ void DMA_schedule(void) { - if (dma_bh_scheduled) { + if (dma_controllers[0].dma_bh_scheduled || + dma_controllers[1].dma_bh_scheduled) { qemu_notify_event(); } } @@ -552,6 +544,8 @@ static void dma_init2(I8257State *d, int base, int ds= hift, for (i =3D 0; i < ARRAY_SIZE (d->regs); ++i) { d->regs[i].transfer_handler =3D i8257_phony_handler; } + + d->dma_bh =3D qemu_bh_new(i8257_dma_run, d); } =20 static const VMStateDescription vmstate_i8257_regs =3D { @@ -572,7 +566,8 @@ static const VMStateDescription vmstate_i8257_regs =3D= { =20 static int i8257_post_load(void *opaque, int version_id) { - i8257_dma_run(); + I8257State *d =3D opaque; + i8257_dma_run(d); =20 return 0; } @@ -599,6 +594,4 @@ void DMA_init(ISABus *bus, int high_page_enable) dma_init2(&dma_controllers[1], 0xc0, 1, 0x88, high_page_enable ? 0x4= 88 : -1); vmstate_register (NULL, 0, &vmstate_dma, &dma_controllers[0]); vmstate_register (NULL, 1, &vmstate_dma, &dma_controllers[1]); - - dma_bh =3D qemu_bh_new(i8257_dma_run_bh, NULL); } --=20 2.4.3