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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 04/15] target-arm: Update arm_generate_debug_exceptions() to handle EL2/EL3
Date: Tue,  9 Feb 2016 18:42:54 +0000	[thread overview]
Message-ID: <1455043385-24250-5-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1455043385-24250-1-git-send-email-peter.maydell@linaro.org>

The arm_generate_debug_exceptions() function as originally implemented
assumes no EL2 or EL3. Since we now have much more of an implementation
of those now, fix this assumption.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1454506721-11843-5-git-send-email-peter.maydell@linaro.org
---
 target-arm/cpu.h | 48 +++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 43 insertions(+), 5 deletions(-)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index cf2df50..0fb79d0 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1742,9 +1742,7 @@ typedef enum ARMASIdx {
     ARMASIdx_S = 1,
 } ARMASIdx;
 
-/* Return the Exception Level targeted by debug exceptions;
- * currently always EL1 since we don't implement EL2 or EL3.
- */
+/* Return the Exception Level targeted by debug exceptions. */
 static inline int arm_debug_target_el(CPUARMState *env)
 {
     bool secure = arm_is_secure(env);
@@ -1767,6 +1765,14 @@ static inline int arm_debug_target_el(CPUARMState *env)
 
 static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
 {
+    if (arm_is_secure(env)) {
+        /* MDCR_EL3.SDD disables debug events from Secure state */
+        if (extract32(env->cp15.mdcr_el3, 16, 1) != 0
+            || arm_current_el(env) == 3) {
+            return false;
+        }
+    }
+
     if (arm_current_el(env) == arm_debug_target_el(env)) {
         if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0)
             || (env->daif & PSTATE_D)) {
@@ -1778,10 +1784,42 @@ static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
 
 static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
 {
-    if (arm_current_el(env) == 0 && arm_el_is_aa64(env, 1)) {
+    int el = arm_current_el(env);
+
+    if (el == 0 && arm_el_is_aa64(env, 1)) {
         return aa64_generate_debug_exceptions(env);
     }
-    return arm_current_el(env) != 2;
+
+    if (arm_is_secure(env)) {
+        int spd;
+
+        if (el == 0 && (env->cp15.sder & 1)) {
+            /* SDER.SUIDEN means debug exceptions from Secure EL0
+             * are always enabled. Otherwise they are controlled by
+             * SDCR.SPD like those from other Secure ELs.
+             */
+            return true;
+        }
+
+        spd = extract32(env->cp15.mdcr_el3, 14, 2);
+        switch (spd) {
+        case 1:
+            /* SPD == 0b01 is reserved, but behaves as 0b00. */
+        case 0:
+            /* For 0b00 we return true if external secure invasive debug
+             * is enabled. On real hardware this is controlled by external
+             * signals to the core. QEMU always permits debug, and behaves
+             * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high.
+             */
+            return true;
+        case 2:
+            return false;
+        case 3:
+            return true;
+        }
+    }
+
+    return el != 2;
 }
 
 /* Return true if debugging exceptions are currently enabled.
-- 
1.9.1

  parent reply	other threads:[~2016-02-09 18:43 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-02-09 18:42 [Qemu-devel] [PULL 00/15] target-arm queue Peter Maydell
2016-02-09 18:42 ` [Qemu-devel] [PULL 01/15] target-arm: Fix typo in comment in arm_is_secure_below_el3() Peter Maydell
2016-02-09 18:42 ` [Qemu-devel] [PULL 02/15] target-arm: Implement MDCR_EL3 and SDCR Peter Maydell
2016-02-09 18:42 ` [Qemu-devel] [PULL 03/15] target-arm: Use access_trap_aa32s_el1() for SCR and MVBAR Peter Maydell
2016-02-09 18:42 ` Peter Maydell [this message]
2016-02-09 18:42 ` [Qemu-devel] [PULL 05/15] target-arm: Add isread parameter to CPAccessFns Peter Maydell
2016-02-09 18:42 ` [Qemu-devel] [PULL 06/15] target-arm: Implement NSACR trapping behaviour Peter Maydell
2016-02-09 18:42 ` [Qemu-devel] [PULL 07/15] target-arm: Enable EL3 for Cortex-A53 and Cortex-A57 Peter Maydell
2016-02-09 18:42 ` [Qemu-devel] [PULL 08/15] target-arm: Correct misleading 'is_thumb' syn_* parameter names Peter Maydell
2016-02-09 18:42 ` [Qemu-devel] [PULL 09/15] target-arm: Fix IL bit reported for Thumb coprocessor traps Peter Maydell
2016-02-09 18:43 ` [Qemu-devel] [PULL 10/15] target-arm: Fix IL bit reported for Thumb VFP and Neon traps Peter Maydell
2016-02-09 18:43 ` [Qemu-devel] [PULL 11/15] cpu: Add callback to check architectural watchpoint match Peter Maydell
2016-02-09 18:43 ` [Qemu-devel] [PULL 12/15] target-arm: Implement checking of fired watchpoint Peter Maydell
2016-02-09 18:43 ` [Qemu-devel] [PULL 13/15] sd: limit 'req.cmd' while using as an array index Peter Maydell
2016-02-09 18:43 ` [Qemu-devel] [PULL 14/15] hw/arm/virt: fix max-cpus check Peter Maydell
2016-02-09 18:43 ` [Qemu-devel] [PULL 15/15] bcm2835_property: implement "get board revision" query Peter Maydell
2016-02-11 11:17 ` [Qemu-devel] [PULL 00/15] target-arm queue Peter Maydell

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