* [Qemu-devel] [PATCH v2 01/16] tcg-mips: Always use tcg_debug_assert
2016-02-15 3:42 [Qemu-devel] [PATCH v2 00/16] tcg mips64 and mips r6 improvements Richard Henderson
@ 2016-02-15 3:42 ` Richard Henderson
2016-02-28 23:51 ` Aurelien Jarno
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 02/16] tcg-mips: Move bswap code to a subroutine Richard Henderson
` (16 subsequent siblings)
17 siblings, 1 reply; 20+ messages in thread
From: Richard Henderson @ 2016-02-15 3:42 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, aurelien
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/mips/tcg-target.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 2dc4998..ebb936d 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -128,7 +128,7 @@ static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, tcg_insn_unit *target)
{
/* Let the compiler perform the right-shift as part of the arithmetic. */
ptrdiff_t disp = target - (pc + 1);
- assert(disp == (int16_t)disp);
+ tcg_debug_assert(disp == (int16_t)disp);
return disp & 0xffff;
}
@@ -139,7 +139,7 @@ static inline void reloc_pc16(tcg_insn_unit *pc, tcg_insn_unit *target)
static inline uint32_t reloc_26_val(tcg_insn_unit *pc, tcg_insn_unit *target)
{
- assert((((uintptr_t)pc ^ (uintptr_t)target) & 0xf0000000) == 0);
+ tcg_debug_assert((((uintptr_t)pc ^ (uintptr_t)target) & 0xf0000000) == 0);
return ((uintptr_t)target >> 2) & 0x3ffffff;
}
@@ -151,8 +151,8 @@ static inline void reloc_26(tcg_insn_unit *pc, tcg_insn_unit *target)
static void patch_reloc(tcg_insn_unit *code_ptr, int type,
intptr_t value, intptr_t addend)
{
- assert(type == R_MIPS_PC16);
- assert(addend == 0);
+ tcg_debug_assert(type == R_MIPS_PC16);
+ tcg_debug_assert(addend == 0);
reloc_pc16(code_ptr, (tcg_insn_unit *)value);
}
@@ -433,7 +433,7 @@ static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, void *target)
if ((from ^ dest) & -(1 << 28)) {
return false;
}
- assert((dest & 3) == 0);
+ tcg_debug_assert((dest & 3) == 0);
inst = opc;
inst |= (dest >> 2) & 0x3ffffff;
@@ -808,9 +808,9 @@ static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
TCGReg tmp0 = TCG_TMP0;
TCGReg tmp1 = ret;
- assert(ret != TCG_TMP0);
+ tcg_debug_assert(ret != TCG_TMP0);
if (ret == ah || ret == bh) {
- assert(ret != TCG_TMP1);
+ tcg_debug_assert(ret != TCG_TMP1);
tmp1 = TCG_TMP1;
}
@@ -1471,8 +1471,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_and_i32:
if (c2 && a2 != (uint16_t)a2) {
int msb = ctz32(~a2) - 1;
- assert(use_mips32r2_instructions);
- assert(is_p2m1(a2));
+ tcg_debug_assert(use_mips32r2_instructions);
+ tcg_debug_assert(is_p2m1(a2));
tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0);
break;
}
--
2.5.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [Qemu-devel] [PATCH v2 01/16] tcg-mips: Always use tcg_debug_assert
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 01/16] tcg-mips: Always use tcg_debug_assert Richard Henderson
@ 2016-02-28 23:51 ` Aurelien Jarno
0 siblings, 0 replies; 20+ messages in thread
From: Aurelien Jarno @ 2016-02-28 23:51 UTC (permalink / raw)
To: Richard Henderson; +Cc: mark.cave-ayland, qemu-devel
On 2016-02-15 14:42, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> tcg/mips/tcg-target.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
> index 2dc4998..ebb936d 100644
> --- a/tcg/mips/tcg-target.c
> +++ b/tcg/mips/tcg-target.c
> @@ -128,7 +128,7 @@ static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, tcg_insn_unit *target)
> {
> /* Let the compiler perform the right-shift as part of the arithmetic. */
> ptrdiff_t disp = target - (pc + 1);
> - assert(disp == (int16_t)disp);
> + tcg_debug_assert(disp == (int16_t)disp);
> return disp & 0xffff;
> }
>
> @@ -139,7 +139,7 @@ static inline void reloc_pc16(tcg_insn_unit *pc, tcg_insn_unit *target)
>
> static inline uint32_t reloc_26_val(tcg_insn_unit *pc, tcg_insn_unit *target)
> {
> - assert((((uintptr_t)pc ^ (uintptr_t)target) & 0xf0000000) == 0);
> + tcg_debug_assert((((uintptr_t)pc ^ (uintptr_t)target) & 0xf0000000) == 0);
> return ((uintptr_t)target >> 2) & 0x3ffffff;
> }
>
> @@ -151,8 +151,8 @@ static inline void reloc_26(tcg_insn_unit *pc, tcg_insn_unit *target)
> static void patch_reloc(tcg_insn_unit *code_ptr, int type,
> intptr_t value, intptr_t addend)
> {
> - assert(type == R_MIPS_PC16);
> - assert(addend == 0);
> + tcg_debug_assert(type == R_MIPS_PC16);
> + tcg_debug_assert(addend == 0);
> reloc_pc16(code_ptr, (tcg_insn_unit *)value);
> }
>
> @@ -433,7 +433,7 @@ static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, void *target)
> if ((from ^ dest) & -(1 << 28)) {
> return false;
> }
> - assert((dest & 3) == 0);
> + tcg_debug_assert((dest & 3) == 0);
>
> inst = opc;
> inst |= (dest >> 2) & 0x3ffffff;
> @@ -808,9 +808,9 @@ static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
> TCGReg tmp0 = TCG_TMP0;
> TCGReg tmp1 = ret;
>
> - assert(ret != TCG_TMP0);
> + tcg_debug_assert(ret != TCG_TMP0);
> if (ret == ah || ret == bh) {
> - assert(ret != TCG_TMP1);
> + tcg_debug_assert(ret != TCG_TMP1);
> tmp1 = TCG_TMP1;
> }
>
> @@ -1471,8 +1471,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
> case INDEX_op_and_i32:
> if (c2 && a2 != (uint16_t)a2) {
> int msb = ctz32(~a2) - 1;
> - assert(use_mips32r2_instructions);
> - assert(is_p2m1(a2));
> + tcg_debug_assert(use_mips32r2_instructions);
> + tcg_debug_assert(is_p2m1(a2));
> tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0);
> break;
> }
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH v2 02/16] tcg-mips: Move bswap code to a subroutine
2016-02-15 3:42 [Qemu-devel] [PATCH v2 00/16] tcg mips64 and mips r6 improvements Richard Henderson
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 01/16] tcg-mips: Always use tcg_debug_assert Richard Henderson
@ 2016-02-15 3:42 ` Richard Henderson
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 03/16] tcg-mips: Add mips64 opcodes Richard Henderson
` (15 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Richard Henderson @ 2016-02-15 3:42 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, aurelien
Without the mips32r2 instructions to perform swapping, bswap is quite large,
dominating the size of each reverse-endian qemu_ld/qemu_st operation.
Create a subroutine in the prologue block. The subroutine requires extra
reserved registers (TCG_TMP[23]). Using these within qemu_ld means that
we need not place additional restrictions on the qemu_ld outputs.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/mips/tcg-target.c | 207 +++++++++++++++++++++++++++++++++-----------------
tcg/mips/tcg-target.h | 2 +-
2 files changed, 139 insertions(+), 70 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index ebb936d..3f33cca 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -75,6 +75,8 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
#define TCG_TMP0 TCG_REG_AT
#define TCG_TMP1 TCG_REG_T9
+#define TCG_TMP2 TCG_REG_T8
+#define TCG_TMP3 TCG_REG_T7
/* check if we really need so many registers :P */
static const TCGReg tcg_target_reg_alloc_order[] = {
@@ -123,6 +125,7 @@ static const TCGReg tcg_target_call_oarg_regs[2] = {
};
static tcg_insn_unit *tb_ret_addr;
+static tcg_insn_unit *bswap32_addr;
static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, tcg_insn_unit *target)
{
@@ -178,12 +181,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
ct->ct |= TCG_CT_REG;
tcg_regset_set(ct->u.regs, 0xffffffff);
break;
- case 'L': /* qemu_ld output arg constraint */
- ct->ct |= TCG_CT_REG;
- tcg_regset_set(ct->u.regs, 0xffffffff);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_V0);
- break;
- case 'l': /* qemu_ld input arg constraint */
+ case 'L': /* qemu_ld input arg constraint */
ct->ct |= TCG_CT_REG;
tcg_regset_set(ct->u.regs, 0xffffffff);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
@@ -505,29 +503,22 @@ static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg)
}
}
-static inline void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg)
+static void tcg_out_bswap_subr(TCGContext *s, tcg_insn_unit *sub)
+{
+ bool ok = tcg_out_opc_jmp(s, OPC_JAL, sub);
+ tcg_debug_assert(ok);
+}
+
+static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg)
{
if (use_mips32r2_instructions) {
tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
} else {
- /* ret and arg must be different and can't be register at */
- if (ret == arg || ret == TCG_TMP0 || arg == TCG_TMP0) {
- tcg_abort();
- }
-
- tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
-
- tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 24);
- tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0);
-
- tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, arg, 0xff00);
- tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8);
- tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0);
-
- tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8);
- tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0xff00);
- tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0);
+ tcg_out_bswap_subr(s, bswap32_addr);
+ /* delay slot -- never omit the insn, like tcg_out_mov might. */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
+ tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
}
}
@@ -1026,7 +1017,7 @@ static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah)
}
/* Perform the tlb comparison operation. The complete host address is
- placed in BASE. Clobbers AT, T0, A0. */
+ placed in BASE. Clobbers TMP0, TMP1, A0. */
static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
TCGReg addrh, TCGMemOpIdx oi,
tcg_insn_unit *label_ptr[2], bool is_load)
@@ -1202,46 +1193,72 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
}
#endif
-static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
+static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
TCGReg base, TCGMemOp opc)
{
switch (opc & (MO_SSIZE | MO_BSWAP)) {
case MO_UB:
- tcg_out_opc_imm(s, OPC_LBU, datalo, base, 0);
+ tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
break;
case MO_SB:
- tcg_out_opc_imm(s, OPC_LB, datalo, base, 0);
+ tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
break;
case MO_UW | MO_BSWAP:
tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
- tcg_out_bswap16(s, datalo, TCG_TMP1);
+ tcg_out_bswap16(s, lo, TCG_TMP1);
break;
case MO_UW:
- tcg_out_opc_imm(s, OPC_LHU, datalo, base, 0);
+ tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
break;
case MO_SW | MO_BSWAP:
tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
- tcg_out_bswap16s(s, datalo, TCG_TMP1);
+ tcg_out_bswap16s(s, lo, TCG_TMP1);
break;
case MO_SW:
- tcg_out_opc_imm(s, OPC_LH, datalo, base, 0);
+ tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
break;
case MO_UL | MO_BSWAP:
- tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 0);
- tcg_out_bswap32(s, datalo, TCG_TMP1);
+ if (use_mips32r2_instructions) {
+ tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
+ tcg_out_bswap32(s, lo, lo);
+ } else {
+ tcg_out_bswap_subr(s, bswap32_addr);
+ /* delay slot */
+ tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
+ tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3);
+ }
break;
case MO_UL:
- tcg_out_opc_imm(s, OPC_LW, datalo, base, 0);
+ tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
break;
case MO_Q | MO_BSWAP:
- tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, HI_OFF);
- tcg_out_bswap32(s, datalo, TCG_TMP1);
- tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, LO_OFF);
- tcg_out_bswap32(s, datahi, TCG_TMP1);
+ if (use_mips32r2_instructions) {
+ tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
+ tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4);
+ tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0);
+ tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1);
+ tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16);
+ tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16);
+ } else {
+ tcg_out_bswap_subr(s, bswap32_addr);
+ /* delay slot */
+ tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
+ tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4);
+ tcg_out_bswap_subr(s, bswap32_addr);
+ /* delay slot */
+ tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3);
+ tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3);
+ }
break;
case MO_Q:
- tcg_out_opc_imm(s, OPC_LW, datalo, base, LO_OFF);
- tcg_out_opc_imm(s, OPC_LW, datahi, base, HI_OFF);
+ /* Prefer to load from offset 0 first, but allow for overlap. */
+ if (MIPS_BE ? hi != base : lo == base) {
+ tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
+ tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
+ } else {
+ tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
+ tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
+ }
break;
default:
tcg_abort();
@@ -1257,9 +1274,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
#if defined(CONFIG_SOFTMMU)
tcg_insn_unit *label_ptr[2];
#endif
- /* Note that we've eliminated V0 from the output registers,
- so we won't overwrite the base register during loading. */
- TCGReg base = TCG_REG_V0;
+ TCGReg base = TCG_REG_A0;
data_regl = *args++;
data_regh = (is_64 ? *args++ : 0);
@@ -1286,40 +1301,54 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
#endif
}
-static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
+static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
TCGReg base, TCGMemOp opc)
{
+ /* Don't clutter the code below with checks to avoid bswapping ZERO. */
+ if ((lo | hi) == 0) {
+ opc &= ~MO_BSWAP;
+ }
+
switch (opc & (MO_SIZE | MO_BSWAP)) {
case MO_8:
- tcg_out_opc_imm(s, OPC_SB, datalo, base, 0);
+ tcg_out_opc_imm(s, OPC_SB, lo, base, 0);
break;
case MO_16 | MO_BSWAP:
- tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, datalo, 0xffff);
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, lo, 0xffff);
tcg_out_bswap16(s, TCG_TMP1, TCG_TMP1);
- datalo = TCG_TMP1;
+ lo = TCG_TMP1;
/* FALLTHRU */
case MO_16:
- tcg_out_opc_imm(s, OPC_SH, datalo, base, 0);
+ tcg_out_opc_imm(s, OPC_SH, lo, base, 0);
break;
case MO_32 | MO_BSWAP:
- tcg_out_bswap32(s, TCG_TMP1, datalo);
- datalo = TCG_TMP1;
+ tcg_out_bswap32(s, TCG_TMP3, lo);
+ lo = TCG_TMP3;
/* FALLTHRU */
case MO_32:
- tcg_out_opc_imm(s, OPC_SW, datalo, base, 0);
+ tcg_out_opc_imm(s, OPC_SW, lo, base, 0);
break;
case MO_64 | MO_BSWAP:
- tcg_out_bswap32(s, TCG_TMP1, datalo);
- tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, HI_OFF);
- tcg_out_bswap32(s, TCG_TMP1, datahi);
- tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, LO_OFF);
+ if (use_mips32r2_instructions) {
+ tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi);
+ tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo);
+ tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16);
+ tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16);
+ tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0);
+ tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4);
+ } else {
+ tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi);
+ tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0);
+ tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo);
+ tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4);
+ }
break;
case MO_64:
- tcg_out_opc_imm(s, OPC_SW, datalo, base, LO_OFF);
- tcg_out_opc_imm(s, OPC_SW, datahi, base, HI_OFF);
+ tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0);
+ tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4);
break;
default:
@@ -1330,12 +1359,13 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
{
TCGReg addr_regl, addr_regh __attribute__((unused));
- TCGReg data_regl, data_regh, base;
+ TCGReg data_regl, data_regh;
TCGMemOpIdx oi;
TCGMemOp opc;
#if defined(CONFIG_SOFTMMU)
tcg_insn_unit *label_ptr[2];
#endif
+ TCGReg base = TCG_REG_A0;
data_regl = *args++;
data_regh = (is_64 ? *args++ : 0);
@@ -1345,9 +1375,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
opc = get_memop(oi);
#if defined(CONFIG_SOFTMMU)
- /* Note that we eliminated the helper's address argument,
- so we can reuse that for the base. */
- base = (TARGET_LONG_BITS == 32 ? TCG_REG_A1 : TCG_REG_A2);
tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0);
tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
add_qemu_ldst_label(s, 0, oi, data_regl, data_regh, addr_regl, addr_regh,
@@ -1356,7 +1383,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
if (guest_base == 0) {
base = addr_regl;
} else {
- base = TCG_REG_A0;
if (guest_base == (int16_t)guest_base) {
tcg_out_opc_imm(s, OPC_ADDIU, base, addr_regl, guest_base);
} else {
@@ -1589,8 +1615,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_bswap32_i32:
- tcg_out_opc_reg(s, OPC_WSBH, a0, 0, a1);
- tcg_out_opc_sa(s, OPC_ROTR, a0, a0, 16);
+ tcg_out_bswap32(s, a0, a1);
break;
case INDEX_op_deposit_i32:
@@ -1707,14 +1732,14 @@ static const TCGTargetOpDef mips_op_defs[] = {
{ INDEX_op_brcond2_i32, { "rZ", "rZ", "rZ", "rZ" } },
#if TARGET_LONG_BITS == 32
- { INDEX_op_qemu_ld_i32, { "L", "lZ" } },
+ { INDEX_op_qemu_ld_i32, { "r", "LZ" } },
{ INDEX_op_qemu_st_i32, { "SZ", "SZ" } },
- { INDEX_op_qemu_ld_i64, { "L", "L", "lZ" } },
+ { INDEX_op_qemu_ld_i64, { "r", "r", "LZ" } },
{ INDEX_op_qemu_st_i64, { "SZ", "SZ", "SZ" } },
#else
- { INDEX_op_qemu_ld_i32, { "L", "lZ", "lZ" } },
+ { INDEX_op_qemu_ld_i32, { "r", "LZ", "LZ" } },
{ INDEX_op_qemu_st_i32, { "SZ", "SZ", "SZ" } },
- { INDEX_op_qemu_ld_i64, { "L", "L", "lZ", "lZ" } },
+ { INDEX_op_qemu_ld_i64, { "r", "r", "LZ", "LZ" } },
{ INDEX_op_qemu_st_i64, { "SZ", "SZ", "SZ", "SZ" } },
#endif
{ -1 },
@@ -1812,6 +1837,16 @@ static void tcg_target_detect_isa(void)
sigaction(SIGILL, &sa_old, NULL);
}
+static tcg_insn_unit *align_code_ptr(TCGContext *s)
+{
+ uintptr_t p = (uintptr_t)s->code_ptr;
+ if (p & 15) {
+ p = (p + 15) & -16;
+ s->code_ptr = (void *)p;
+ }
+ return s->code_ptr;
+}
+
/* Generate global QEMU prologue and epilogue code */
static void tcg_target_qemu_prologue(TCGContext *s)
{
@@ -1846,7 +1881,39 @@ static void tcg_target_qemu_prologue(TCGContext *s)
}
tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
+ /* delay slot */
tcg_out_addi(s, TCG_REG_SP, frame_size);
+
+ if (use_mips32r2_instructions) {
+ return;
+ }
+
+ /* Bswap subroutine: Input in TCG_TMP0, output in TCG_TMP3;
+ clobbers TCG_TMP1, TCG_TMP2. */
+
+ /*
+ * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd.
+ */
+ bswap32_addr = align_code_ptr(s);
+ /* t3 = (ssss)d000 */
+ tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24);
+ /* t1 = 000a */
+ tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24);
+ /* t2 = 00c0 */
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
+ /* t3 = d00a */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
+ /* t1 = 0abc */
+ tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
+ /* t2 = 0c00 */
+ tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
+ /* t1 = 00b0 */
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
+ /* t3 = dc0a */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
+ tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
+ /* t3 = dcba -- delay slot */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
}
static void tcg_target_init(TCGContext *s)
@@ -1877,6 +1944,8 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */
tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */
tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */
+ tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */
+ tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index b1cda37..387b96d 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -116,11 +116,11 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_muls2_i32 (!use_mips32r6_instructions)
#define TCG_TARGET_HAS_muluh_i32 1
#define TCG_TARGET_HAS_mulsh_i32 1
+#define TCG_TARGET_HAS_bswap32_i32 1
/* optional instructions detected at runtime */
#define TCG_TARGET_HAS_movcond_i32 use_movnz_instructions
#define TCG_TARGET_HAS_bswap16_i32 use_mips32r2_instructions
-#define TCG_TARGET_HAS_bswap32_i32 use_mips32r2_instructions
#define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions
#define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions
#define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions
--
2.5.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH v2 03/16] tcg-mips: Add mips64 opcodes
2016-02-15 3:42 [Qemu-devel] [PATCH v2 00/16] tcg mips64 and mips r6 improvements Richard Henderson
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 01/16] tcg-mips: Always use tcg_debug_assert Richard Henderson
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 02/16] tcg-mips: Move bswap code to a subroutine Richard Henderson
@ 2016-02-15 3:42 ` Richard Henderson
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 04/16] tcg-mips: Support 64-bit opcodes Richard Henderson
` (14 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Richard Henderson @ 2016-02-15 3:42 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, aurelien
Since the mips manual tables are in octal, reorg all of the opcodes
into that format for clarity. Note that the 64-bit opcodes are as
yet unused.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/mips/tcg-target.c | 191 +++++++++++++++++++++++++++++++-------------------
1 file changed, 117 insertions(+), 74 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 3f33cca..71de3bb 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -255,80 +255,117 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
/* instruction opcodes */
typedef enum {
- OPC_J = 0x02 << 26,
- OPC_JAL = 0x03 << 26,
- OPC_BEQ = 0x04 << 26,
- OPC_BNE = 0x05 << 26,
- OPC_BLEZ = 0x06 << 26,
- OPC_BGTZ = 0x07 << 26,
- OPC_ADDIU = 0x09 << 26,
- OPC_SLTI = 0x0A << 26,
- OPC_SLTIU = 0x0B << 26,
- OPC_ANDI = 0x0C << 26,
- OPC_ORI = 0x0D << 26,
- OPC_XORI = 0x0E << 26,
- OPC_LUI = 0x0F << 26,
- OPC_LB = 0x20 << 26,
- OPC_LH = 0x21 << 26,
- OPC_LW = 0x23 << 26,
- OPC_LBU = 0x24 << 26,
- OPC_LHU = 0x25 << 26,
- OPC_LWU = 0x27 << 26,
- OPC_SB = 0x28 << 26,
- OPC_SH = 0x29 << 26,
- OPC_SW = 0x2B << 26,
-
- OPC_SPECIAL = 0x00 << 26,
- OPC_SLL = OPC_SPECIAL | 0x00,
- OPC_SRL = OPC_SPECIAL | 0x02,
- OPC_ROTR = OPC_SPECIAL | (0x01 << 21) | 0x02,
- OPC_SRA = OPC_SPECIAL | 0x03,
- OPC_SLLV = OPC_SPECIAL | 0x04,
- OPC_SRLV = OPC_SPECIAL | 0x06,
- OPC_ROTRV = OPC_SPECIAL | (0x01 << 6) | 0x06,
- OPC_SRAV = OPC_SPECIAL | 0x07,
- OPC_JR_R5 = OPC_SPECIAL | 0x08,
- OPC_JALR = OPC_SPECIAL | 0x09,
- OPC_MOVZ = OPC_SPECIAL | 0x0A,
- OPC_MOVN = OPC_SPECIAL | 0x0B,
- OPC_MFHI = OPC_SPECIAL | 0x10,
- OPC_MFLO = OPC_SPECIAL | 0x12,
- OPC_MULT = OPC_SPECIAL | 0x18,
- OPC_MUL_R6 = OPC_SPECIAL | (0x02 << 6) | 0x18,
- OPC_MUH = OPC_SPECIAL | (0x03 << 6) | 0x18,
- OPC_MULTU = OPC_SPECIAL | 0x19,
- OPC_MULU = OPC_SPECIAL | (0x02 << 6) | 0x19,
- OPC_MUHU = OPC_SPECIAL | (0x03 << 6) | 0x19,
- OPC_DIV = OPC_SPECIAL | 0x1A,
- OPC_DIV_R6 = OPC_SPECIAL | (0x02 << 6) | 0x1A,
- OPC_MOD = OPC_SPECIAL | (0x03 << 6) | 0x1A,
- OPC_DIVU = OPC_SPECIAL | 0x1B,
- OPC_DIVU_R6 = OPC_SPECIAL | (0x02 << 6) | 0x1B,
- OPC_MODU = OPC_SPECIAL | (0x03 << 6) | 0x1B,
- OPC_ADDU = OPC_SPECIAL | 0x21,
- OPC_SUBU = OPC_SPECIAL | 0x23,
- OPC_AND = OPC_SPECIAL | 0x24,
- OPC_OR = OPC_SPECIAL | 0x25,
- OPC_XOR = OPC_SPECIAL | 0x26,
- OPC_NOR = OPC_SPECIAL | 0x27,
- OPC_SLT = OPC_SPECIAL | 0x2A,
- OPC_SLTU = OPC_SPECIAL | 0x2B,
- OPC_SELEQZ = OPC_SPECIAL | 0x35,
- OPC_SELNEZ = OPC_SPECIAL | 0x37,
-
- OPC_REGIMM = 0x01 << 26,
- OPC_BLTZ = OPC_REGIMM | (0x00 << 16),
- OPC_BGEZ = OPC_REGIMM | (0x01 << 16),
-
- OPC_SPECIAL2 = 0x1c << 26,
- OPC_MUL_R5 = OPC_SPECIAL2 | 0x002,
-
- OPC_SPECIAL3 = 0x1f << 26,
- OPC_EXT = OPC_SPECIAL3 | 0x000,
- OPC_INS = OPC_SPECIAL3 | 0x004,
- OPC_WSBH = OPC_SPECIAL3 | 0x0a0,
- OPC_SEB = OPC_SPECIAL3 | 0x420,
- OPC_SEH = OPC_SPECIAL3 | 0x620,
+ OPC_J = 002 << 26,
+ OPC_JAL = 003 << 26,
+ OPC_BEQ = 004 << 26,
+ OPC_BNE = 005 << 26,
+ OPC_BLEZ = 006 << 26,
+ OPC_BGTZ = 007 << 26,
+ OPC_ADDIU = 011 << 26,
+ OPC_SLTI = 012 << 26,
+ OPC_SLTIU = 013 << 26,
+ OPC_ANDI = 014 << 26,
+ OPC_ORI = 015 << 26,
+ OPC_XORI = 016 << 26,
+ OPC_LUI = 017 << 26,
+ OPC_DADDIU = 031 << 26,
+ OPC_LB = 040 << 26,
+ OPC_LH = 041 << 26,
+ OPC_LW = 043 << 26,
+ OPC_LBU = 044 << 26,
+ OPC_LHU = 045 << 26,
+ OPC_LWU = 047 << 26,
+ OPC_SB = 050 << 26,
+ OPC_SH = 051 << 26,
+ OPC_SW = 053 << 26,
+ OPC_LD = 067 << 26,
+ OPC_SD = 077 << 26,
+
+ OPC_SPECIAL = 000 << 26,
+ OPC_SLL = OPC_SPECIAL | 000,
+ OPC_SRL = OPC_SPECIAL | 002,
+ OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21),
+ OPC_SRA = OPC_SPECIAL | 003,
+ OPC_SLLV = OPC_SPECIAL | 004,
+ OPC_SRLV = OPC_SPECIAL | 006,
+ OPC_ROTRV = OPC_SPECIAL | 006 | 0100,
+ OPC_SRAV = OPC_SPECIAL | 007,
+ OPC_JR_R5 = OPC_SPECIAL | 010,
+ OPC_JALR = OPC_SPECIAL | 011,
+ OPC_MOVZ = OPC_SPECIAL | 012,
+ OPC_MOVN = OPC_SPECIAL | 013,
+ OPC_MFHI = OPC_SPECIAL | 020,
+ OPC_MFLO = OPC_SPECIAL | 022,
+ OPC_DSLLV = OPC_SPECIAL | 024,
+ OPC_DSRLV = OPC_SPECIAL | 026,
+ OPC_DROTRV = OPC_SPECIAL | 026 | 0100,
+ OPC_DSRAV = OPC_SPECIAL | 027,
+ OPC_MULT = OPC_SPECIAL | 030,
+ OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200,
+ OPC_MUH = OPC_SPECIAL | 030 | 0300,
+ OPC_MULTU = OPC_SPECIAL | 031,
+ OPC_MULU = OPC_SPECIAL | 031 | 0200,
+ OPC_MUHU = OPC_SPECIAL | 031 | 0300,
+ OPC_DIV = OPC_SPECIAL | 032,
+ OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200,
+ OPC_MOD = OPC_SPECIAL | 032 | 0300,
+ OPC_DIVU = OPC_SPECIAL | 033,
+ OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200,
+ OPC_MODU = OPC_SPECIAL | 033 | 0300,
+ OPC_DMULT = OPC_SPECIAL | 034,
+ OPC_DMUL = OPC_SPECIAL | 034 | 0200,
+ OPC_DMUH = OPC_SPECIAL | 034 | 0300,
+ OPC_DMULTU = OPC_SPECIAL | 035,
+ OPC_DMULU = OPC_SPECIAL | 035 | 0200,
+ OPC_DMUHU = OPC_SPECIAL | 035 | 0300,
+ OPC_DDIV = OPC_SPECIAL | 036,
+ OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200,
+ OPC_DMOD = OPC_SPECIAL | 036 | 0300,
+ OPC_DDIVU = OPC_SPECIAL | 037,
+ OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200,
+ OPC_DMODU = OPC_SPECIAL | 037 | 0300,
+ OPC_ADDU = OPC_SPECIAL | 041,
+ OPC_SUBU = OPC_SPECIAL | 043,
+ OPC_AND = OPC_SPECIAL | 044,
+ OPC_OR = OPC_SPECIAL | 045,
+ OPC_XOR = OPC_SPECIAL | 046,
+ OPC_NOR = OPC_SPECIAL | 047,
+ OPC_SLT = OPC_SPECIAL | 052,
+ OPC_SLTU = OPC_SPECIAL | 053,
+ OPC_DADDU = OPC_SPECIAL | 055,
+ OPC_DSUBU = OPC_SPECIAL | 057,
+ OPC_SELEQZ = OPC_SPECIAL | 065,
+ OPC_SELNEZ = OPC_SPECIAL | 067,
+ OPC_DSLL = OPC_SPECIAL | 070,
+ OPC_DSRL = OPC_SPECIAL | 072,
+ OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21),
+ OPC_DSRA = OPC_SPECIAL | 073,
+ OPC_DSLL32 = OPC_SPECIAL | 074,
+ OPC_DSRL32 = OPC_SPECIAL | 076,
+ OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21),
+ OPC_DSRA32 = OPC_SPECIAL | 077,
+
+ OPC_REGIMM = 001 << 26,
+ OPC_BLTZ = OPC_REGIMM | (000 << 16),
+ OPC_BGEZ = OPC_REGIMM | (001 << 16),
+
+ OPC_SPECIAL2 = 034 << 26,
+ OPC_MUL_R5 = OPC_SPECIAL2 | 002,
+
+ OPC_SPECIAL3 = 037 << 26,
+ OPC_EXT = OPC_SPECIAL3 | 000,
+ OPC_DEXTM = OPC_SPECIAL3 | 001,
+ OPC_DEXTU = OPC_SPECIAL3 | 002,
+ OPC_DEXT = OPC_SPECIAL3 | 003,
+ OPC_INS = OPC_SPECIAL3 | 004,
+ OPC_DINSM = OPC_SPECIAL3 | 005,
+ OPC_DINSU = OPC_SPECIAL3 | 006,
+ OPC_DINS = OPC_SPECIAL3 | 007,
+ OPC_WSBH = OPC_SPECIAL3 | 00240,
+ OPC_DSBH = OPC_SPECIAL3 | 00244,
+ OPC_DSHD = OPC_SPECIAL3 | 00544,
+ OPC_SEB = OPC_SPECIAL3 | 02040,
+ OPC_SEH = OPC_SPECIAL3 | 03040,
/* MIPS r6 doesn't have JR, JALR should be used instead */
OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5,
@@ -338,6 +375,12 @@ typedef enum {
* backwards-compatible at the assembly level.
*/
OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5,
+
+ /* Aliases for convenience. */
+ ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU,
+ ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU,
+ ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32
+ ? OPC_SRL : OPC_DSRL,
} MIPSInsn;
/*
--
2.5.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH v2 04/16] tcg-mips: Support 64-bit opcodes
2016-02-15 3:42 [Qemu-devel] [PATCH v2 00/16] tcg mips64 and mips r6 improvements Richard Henderson
` (2 preceding siblings ...)
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 03/16] tcg-mips: Add mips64 opcodes Richard Henderson
@ 2016-02-15 3:42 ` Richard Henderson
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 05/16] tcg-mips: Add bswap32u and bswap64 Richard Henderson
` (13 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Richard Henderson @ 2016-02-15 3:42 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, aurelien
Bulk patch adding 64-bit opcodes into tcg_out_op. Note that
mips64 is as yet neither complete nor enabled.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/mips/tcg-target.c | 322 ++++++++++++++++++++++++++++++++++++++++++++++++--
tcg/mips/tcg-target.h | 41 +++++++
2 files changed, 353 insertions(+), 10 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 71de3bb..5ce52ad 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -429,6 +429,21 @@ static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt,
tcg_out32(s, inst);
}
+static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm,
+ MIPSInsn oph, TCGReg rt, TCGReg rs,
+ int msb, int lsb)
+{
+ if (lsb >= 32) {
+ opc = oph;
+ msb -= 32;
+ lsb -= 32;
+ } else if (msb >= 32) {
+ opc = opm;
+ msb -= 32;
+ }
+ tcg_out_opc_bf(s, opc, rt, rs, msb, lsb);
+}
+
/*
* Type branch
*/
@@ -459,6 +474,18 @@ static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc,
}
+static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2,
+ TCGReg rd, TCGReg rt, TCGArg sa)
+{
+ int32_t inst;
+
+ inst = (sa & 32 ? opc2 : opc1);
+ inst |= (rt & 0x1F) << 16;
+ inst |= (rd & 0x1F) << 11;
+ inst |= (sa & 0x1F) << 6;
+ tcg_out32(s, inst);
+}
+
/*
* Type jump.
* Returns true if the branch was in range and the insn was emitted.
@@ -487,6 +514,21 @@ static inline void tcg_out_nop(TCGContext *s)
tcg_out32(s, 0);
}
+static inline void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
+{
+ tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa);
+}
+
+static inline void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
+{
+ tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa);
+}
+
+static inline void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
+{
+ tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa);
+}
+
static inline void tcg_out_mov(TCGContext *s, TCGType type,
TCGReg ret, TCGReg arg)
{
@@ -565,6 +607,27 @@ static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg)
}
}
+static void tcg_out_bswap32u(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ if (use_mips32r2_instructions) {
+ tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
+ tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
+ tcg_out_dsrl(s, ret, ret, 32);
+ } else {
+ abort();
+ }
+}
+
+static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ if (use_mips32r2_instructions) {
+ tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
+ tcg_out_opc_reg(s, OPC_DSHD, ret, 0, arg);
+ } else {
+ abort();
+ }
+}
+
static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
{
if (use_mips32r2_instructions) {
@@ -585,6 +648,16 @@ static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg)
}
}
+static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+ if (use_mips32r2_instructions) {
+ tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0);
+ } else {
+ tcg_out_dsll(s, ret, arg, 32);
+ tcg_out_dsrl(s, ret, ret, 32);
+ }
+}
+
static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
TCGReg addr, intptr_t ofs)
{
@@ -1454,6 +1527,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
{
TCGReg b0 = TCG_REG_ZERO;
+ a0 = (intptr_t)a0;
if (a0 & ~0xffff) {
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff);
b0 = TCG_REG_V0;
@@ -1487,28 +1561,45 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_ld8u_i32:
+ case INDEX_op_ld8u_i64:
i1 = OPC_LBU;
goto do_ldst;
case INDEX_op_ld8s_i32:
+ case INDEX_op_ld8s_i64:
i1 = OPC_LB;
goto do_ldst;
case INDEX_op_ld16u_i32:
+ case INDEX_op_ld16u_i64:
i1 = OPC_LHU;
goto do_ldst;
case INDEX_op_ld16s_i32:
+ case INDEX_op_ld16s_i64:
i1 = OPC_LH;
goto do_ldst;
case INDEX_op_ld_i32:
+ case INDEX_op_ld32s_i64:
i1 = OPC_LW;
goto do_ldst;
+ case INDEX_op_ld32u_i64:
+ i1 = OPC_LWU;
+ goto do_ldst;
+ case INDEX_op_ld_i64:
+ i1 = OPC_LD;
+ goto do_ldst;
case INDEX_op_st8_i32:
+ case INDEX_op_st8_i64:
i1 = OPC_SB;
goto do_ldst;
case INDEX_op_st16_i32:
+ case INDEX_op_st16_i64:
i1 = OPC_SH;
goto do_ldst;
case INDEX_op_st_i32:
+ case INDEX_op_st32_i64:
i1 = OPC_SW;
+ goto do_ldst;
+ case INDEX_op_st_i64:
+ i1 = OPC_SD;
do_ldst:
tcg_out_ldst(s, i1, a0, a1, a2);
break;
@@ -1516,10 +1607,15 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_add_i32:
i1 = OPC_ADDU, i2 = OPC_ADDIU;
goto do_binary;
+ case INDEX_op_add_i64:
+ i1 = OPC_DADDU, i2 = OPC_DADDIU;
+ goto do_binary;
case INDEX_op_or_i32:
+ case INDEX_op_or_i64:
i1 = OPC_OR, i2 = OPC_ORI;
goto do_binary;
case INDEX_op_xor_i32:
+ case INDEX_op_xor_i64:
i1 = OPC_XOR, i2 = OPC_XORI;
do_binary:
if (c2) {
@@ -1531,12 +1627,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_sub_i32:
+ i1 = OPC_SUBU, i2 = OPC_ADDIU;
+ goto do_subtract;
+ case INDEX_op_sub_i64:
+ i1 = OPC_DSUBU, i2 = OPC_DADDIU;
+ do_subtract:
if (c2) {
- tcg_out_opc_imm(s, OPC_ADDIU, a0, a1, -a2);
+ tcg_out_opc_imm(s, i2, a0, a1, -a2);
break;
}
- i1 = OPC_SUBU;
- goto do_binary;
+ goto do_binaryv;
case INDEX_op_and_i32:
if (c2 && a2 != (uint16_t)a2) {
int msb = ctz32(~a2) - 1;
@@ -1547,7 +1647,18 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
i1 = OPC_AND, i2 = OPC_ANDI;
goto do_binary;
+ case INDEX_op_and_i64:
+ if (c2 && a2 != (uint16_t)a2) {
+ int msb = ctz64(~a2) - 1;
+ tcg_debug_assert(use_mips32r2_instructions);
+ tcg_debug_assert(is_p2m1(a2));
+ tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0);
+ break;
+ }
+ i1 = OPC_AND, i2 = OPC_ANDI;
+ goto do_binary;
case INDEX_op_nor_i32:
+ case INDEX_op_nor_i64:
i1 = OPC_NOR;
goto do_binaryv;
@@ -1599,6 +1710,55 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
}
i1 = OPC_DIVU, i2 = OPC_MFHI;
+ goto do_hilo1;
+ case INDEX_op_mul_i64:
+ if (use_mips32r6_instructions) {
+ tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DMULT, i2 = OPC_MFLO;
+ goto do_hilo1;
+ case INDEX_op_mulsh_i64:
+ if (use_mips32r6_instructions) {
+ tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DMULT, i2 = OPC_MFHI;
+ goto do_hilo1;
+ case INDEX_op_muluh_i64:
+ if (use_mips32r6_instructions) {
+ tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DMULTU, i2 = OPC_MFHI;
+ goto do_hilo1;
+ case INDEX_op_div_i64:
+ if (use_mips32r6_instructions) {
+ tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DDIV, i2 = OPC_MFLO;
+ goto do_hilo1;
+ case INDEX_op_divu_i64:
+ if (use_mips32r6_instructions) {
+ tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DDIVU, i2 = OPC_MFLO;
+ goto do_hilo1;
+ case INDEX_op_rem_i64:
+ if (use_mips32r6_instructions) {
+ tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DDIV, i2 = OPC_MFHI;
+ goto do_hilo1;
+ case INDEX_op_remu_i64:
+ if (use_mips32r6_instructions) {
+ tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DDIVU, i2 = OPC_MFHI;
do_hilo1:
tcg_out_opc_reg(s, i1, 0, a1, a2);
tcg_out_opc_reg(s, i2, a0, 0, 0);
@@ -1609,6 +1769,12 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
goto do_hilo2;
case INDEX_op_mulu2_i32:
i1 = OPC_MULTU;
+ goto do_hilo2;
+ case INDEX_op_muls2_i64:
+ i1 = OPC_DMULT;
+ goto do_hilo2;
+ case INDEX_op_mulu2_i64:
+ i1 = OPC_DMULTU;
do_hilo2:
tcg_out_opc_reg(s, i1, 0, a2, args[3]);
tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0);
@@ -1616,20 +1782,46 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_not_i32:
+ case INDEX_op_not_i64:
i1 = OPC_NOR;
goto do_unary;
case INDEX_op_bswap16_i32:
+ case INDEX_op_bswap16_i64:
i1 = OPC_WSBH;
goto do_unary;
case INDEX_op_ext8s_i32:
+ case INDEX_op_ext8s_i64:
i1 = OPC_SEB;
goto do_unary;
case INDEX_op_ext16s_i32:
+ case INDEX_op_ext16s_i64:
i1 = OPC_SEH;
do_unary:
tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1);
break;
+ case INDEX_op_bswap32_i32:
+ tcg_out_bswap32(s, a0, a1);
+ break;
+ case INDEX_op_bswap32_i64:
+ tcg_out_bswap32u(s, a0, a1);
+ break;
+ case INDEX_op_bswap64_i64:
+ tcg_out_bswap64(s, a0, a1);
+ break;
+ case INDEX_op_extrh_i64_i32:
+ tcg_out_dsra(s, a0, a1, 32);
+ break;
+ case INDEX_op_ext32s_i64:
+ case INDEX_op_ext_i32_i64:
+ case INDEX_op_extrl_i64_i32:
+ tcg_out_opc_sa(s, OPC_SLL, a0, a1, 0);
+ break;
+ case INDEX_op_ext32u_i64:
+ case INDEX_op_extu_i32_i64:
+ tcg_out_ext32u(s, a0, a1);
+ break;
+
case INDEX_op_sar_i32:
i1 = OPC_SRAV, i2 = OPC_SRA;
goto do_shift;
@@ -1644,9 +1836,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
do_shift:
if (c2) {
tcg_out_opc_sa(s, i2, a0, a1, a2);
- } else {
- tcg_out_opc_reg(s, i1, a0, a2, a1);
+ break;
}
+ do_shiftv:
+ tcg_out_opc_reg(s, i1, a0, a2, a1);
break;
case INDEX_op_rotl_i32:
if (c2) {
@@ -1656,16 +1849,53 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1);
}
break;
-
- case INDEX_op_bswap32_i32:
- tcg_out_bswap32(s, a0, a1);
+ case INDEX_op_sar_i64:
+ if (c2) {
+ tcg_out_dsra(s, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DSRAV;
+ goto do_shiftv;
+ case INDEX_op_shl_i64:
+ if (c2) {
+ tcg_out_dsll(s, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DSLLV;
+ goto do_shiftv;
+ case INDEX_op_shr_i64:
+ if (c2) {
+ tcg_out_dsrl(s, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DSRLV;
+ goto do_shiftv;
+ case INDEX_op_rotr_i64:
+ if (c2) {
+ tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2);
+ break;
+ }
+ i1 = OPC_DROTRV;
+ goto do_shiftv;
+ case INDEX_op_rotl_i64:
+ if (c2) {
+ tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2);
+ } else {
+ tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2);
+ tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1);
+ }
break;
case INDEX_op_deposit_i32:
tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]);
break;
+ case INDEX_op_deposit_i64:
+ tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2,
+ args[3] + args[4] - 1, args[3]);
+ break;
case INDEX_op_brcond_i32:
+ case INDEX_op_brcond_i64:
tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
break;
case INDEX_op_brcond2_i32:
@@ -1673,10 +1903,12 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_movcond_i32:
+ case INDEX_op_movcond_i64:
tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]);
break;
case INDEX_op_setcond_i32:
+ case INDEX_op_setcond_i64:
tcg_out_setcond(s, args[3], a0, a1, a2);
break;
case INDEX_op_setcond2_i32:
@@ -1706,7 +1938,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
+ case INDEX_op_mov_i64:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
+ case INDEX_op_movi_i64:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
default:
tcg_abort();
@@ -1768,13 +2002,81 @@ static const TCGTargetOpDef mips_op_defs[] = {
{ INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "0" } },
#endif
{ INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
- { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },
+#if TCG_TARGET_REG_BITS == 32
{ INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rN", "rN" } },
{ INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rN", "rN" } },
+ { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },
{ INDEX_op_brcond2_i32, { "rZ", "rZ", "rZ", "rZ" } },
+#endif
-#if TARGET_LONG_BITS == 32
+#if TCG_TARGET_REG_BITS == 64
+ { INDEX_op_ld8u_i64, { "r", "r" } },
+ { INDEX_op_ld8s_i64, { "r", "r" } },
+ { INDEX_op_ld16u_i64, { "r", "r" } },
+ { INDEX_op_ld16s_i64, { "r", "r" } },
+ { INDEX_op_ld32s_i64, { "r", "r" } },
+ { INDEX_op_ld32u_i64, { "r", "r" } },
+ { INDEX_op_ld_i64, { "r", "r" } },
+ { INDEX_op_st8_i64, { "rZ", "r" } },
+ { INDEX_op_st16_i64, { "rZ", "r" } },
+ { INDEX_op_st32_i64, { "rZ", "r" } },
+ { INDEX_op_st_i64, { "rZ", "r" } },
+
+ { INDEX_op_add_i64, { "r", "rZ", "rJ" } },
+ { INDEX_op_mul_i64, { "r", "rZ", "rZ" } },
+#if !use_mips32r6_instructions
+ { INDEX_op_muls2_i64, { "r", "r", "rZ", "rZ" } },
+ { INDEX_op_mulu2_i64, { "r", "r", "rZ", "rZ" } },
+#endif
+ { INDEX_op_mulsh_i64, { "r", "rZ", "rZ" } },
+ { INDEX_op_muluh_i64, { "r", "rZ", "rZ" } },
+ { INDEX_op_div_i64, { "r", "rZ", "rZ" } },
+ { INDEX_op_divu_i64, { "r", "rZ", "rZ" } },
+ { INDEX_op_rem_i64, { "r", "rZ", "rZ" } },
+ { INDEX_op_remu_i64, { "r", "rZ", "rZ" } },
+ { INDEX_op_sub_i64, { "r", "rZ", "rN" } },
+
+ { INDEX_op_and_i64, { "r", "rZ", "rIK" } },
+ { INDEX_op_nor_i64, { "r", "rZ", "rZ" } },
+ { INDEX_op_not_i64, { "r", "rZ" } },
+ { INDEX_op_or_i64, { "r", "rZ", "rI" } },
+ { INDEX_op_xor_i64, { "r", "rZ", "rI" } },
+
+ { INDEX_op_shl_i64, { "r", "rZ", "ri" } },
+ { INDEX_op_shr_i64, { "r", "rZ", "ri" } },
+ { INDEX_op_sar_i64, { "r", "rZ", "ri" } },
+ { INDEX_op_rotr_i64, { "r", "rZ", "ri" } },
+ { INDEX_op_rotl_i64, { "r", "rZ", "ri" } },
+
+ { INDEX_op_bswap16_i64, { "r", "r" } },
+ { INDEX_op_bswap32_i64, { "r", "r" } },
+ { INDEX_op_bswap64_i64, { "r", "r" } },
+
+ { INDEX_op_ext8s_i64, { "r", "rZ" } },
+ { INDEX_op_ext16s_i64, { "r", "rZ" } },
+ { INDEX_op_ext32s_i64, { "r", "rZ" } },
+ { INDEX_op_ext32u_i64, { "r", "rZ" } },
+ { INDEX_op_ext_i32_i64, { "r", "rZ" } },
+ { INDEX_op_extu_i32_i64, { "r", "rZ" } },
+ { INDEX_op_extrl_i64_i32, { "r", "rZ" } },
+ { INDEX_op_extrh_i64_i32, { "r", "rZ" } },
+
+ { INDEX_op_deposit_i64, { "r", "0", "rZ" } },
+
+ { INDEX_op_brcond_i64, { "rZ", "rZ" } },
+#if use_mips32r6_instructions
+ { INDEX_op_movcond_i64, { "r", "rZ", "rZ", "rZ", "rZ" } },
+#else
+ { INDEX_op_movcond_i64, { "r", "rZ", "rZ", "rZ", "0" } },
+#endif
+ { INDEX_op_setcond_i64, { "r", "rZ", "rZ" } },
+
+ { INDEX_op_qemu_ld_i32, { "r", "LZ" } },
+ { INDEX_op_qemu_st_i32, { "SZ", "SZ" } },
+ { INDEX_op_qemu_ld_i64, { "r", "LZ" } },
+ { INDEX_op_qemu_st_i64, { "SZ", "SZ" } },
+#elif TARGET_LONG_BITS == 32
{ INDEX_op_qemu_ld_i32, { "r", "LZ" } },
{ INDEX_op_qemu_st_i32, { "SZ", "SZ" } },
{ INDEX_op_qemu_ld_i64, { "r", "r", "LZ" } },
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index 387b96d..1a9e54c 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -26,6 +26,7 @@
#ifndef TCG_TARGET_MIPS
#define TCG_TARGET_MIPS 1
+#define TCG_TARGET_REG_BITS 32
#define TCG_TARGET_INSN_UNIT_SIZE 4
#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
#define TCG_TARGET_NB_REGS 32
@@ -118,6 +119,29 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_mulsh_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
+#if TCG_TARGET_REG_BITS == 64
+#define TCG_TARGET_HAS_add2_i32 0
+#define TCG_TARGET_HAS_sub2_i32 0
+#define TCG_TARGET_HAS_extrl_i64_i32 1
+#define TCG_TARGET_HAS_extrh_i64_i32 1
+#define TCG_TARGET_HAS_div_i64 1
+#define TCG_TARGET_HAS_rem_i64 1
+#define TCG_TARGET_HAS_not_i64 1
+#define TCG_TARGET_HAS_nor_i64 1
+#define TCG_TARGET_HAS_andc_i64 0
+#define TCG_TARGET_HAS_orc_i64 0
+#define TCG_TARGET_HAS_eqv_i64 0
+#define TCG_TARGET_HAS_nand_i64 0
+#define TCG_TARGET_HAS_add2_i64 0
+#define TCG_TARGET_HAS_sub2_i64 0
+#define TCG_TARGET_HAS_mulu2_i64 (!use_mips32r6_instructions)
+#define TCG_TARGET_HAS_muls2_i64 (!use_mips32r6_instructions)
+#define TCG_TARGET_HAS_muluh_i64 1
+#define TCG_TARGET_HAS_mulsh_i64 1
+#define TCG_TARGET_HAS_ext32s_i64 1
+#define TCG_TARGET_HAS_ext32u_i64 1
+#endif
+
/* optional instructions detected at runtime */
#define TCG_TARGET_HAS_movcond_i32 use_movnz_instructions
#define TCG_TARGET_HAS_bswap16_i32 use_mips32r2_instructions
@@ -126,11 +150,28 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions
#define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions
+#if TCG_TARGET_REG_BITS == 64
+#define TCG_TARGET_HAS_movcond_i64 use_movnz_instructions
+#define TCG_TARGET_HAS_bswap16_i64 use_mips32r2_instructions
+#define TCG_TARGET_HAS_bswap32_i64 use_mips32r2_instructions
+#define TCG_TARGET_HAS_bswap64_i64 use_mips32r2_instructions
+#define TCG_TARGET_HAS_deposit_i64 use_mips32r2_instructions
+#define TCG_TARGET_HAS_ext8s_i64 use_mips32r2_instructions
+#define TCG_TARGET_HAS_ext16s_i64 use_mips32r2_instructions
+#define TCG_TARGET_HAS_rot_i64 use_mips32r2_instructions
+#endif
+
/* optional instructions automatically implemented */
#define TCG_TARGET_HAS_neg_i32 0 /* sub rd, zero, rt */
#define TCG_TARGET_HAS_ext8u_i32 0 /* andi rt, rs, 0xff */
#define TCG_TARGET_HAS_ext16u_i32 0 /* andi rt, rs, 0xffff */
+#if TCG_TARGET_REG_BITS == 64
+#define TCG_TARGET_HAS_neg_i64 0 /* sub rd, zero, rt */
+#define TCG_TARGET_HAS_ext8u_i64 0 /* andi rt, rs, 0xff */
+#define TCG_TARGET_HAS_ext16u_i64 0 /* andi rt, rs, 0xffff */
+#endif
+
#ifdef __OpenBSD__
#include <machine/sysarch.h>
#else
--
2.5.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH v2 05/16] tcg-mips: Add bswap32u and bswap64
2016-02-15 3:42 [Qemu-devel] [PATCH v2 00/16] tcg mips64 and mips r6 improvements Richard Henderson
` (3 preceding siblings ...)
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 04/16] tcg-mips: Support 64-bit opcodes Richard Henderson
@ 2016-02-15 3:42 ` Richard Henderson
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 06/16] tcg-mips: Adjust move functions for mips64 Richard Henderson
` (12 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Richard Henderson @ 2016-02-15 3:42 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, aurelien
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/mips/tcg-target.c | 102 ++++++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 99 insertions(+), 3 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 5ce52ad..88c032c 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -126,6 +126,8 @@ static const TCGReg tcg_target_call_oarg_regs[2] = {
static tcg_insn_unit *tb_ret_addr;
static tcg_insn_unit *bswap32_addr;
+static tcg_insn_unit *bswap32u_addr;
+static tcg_insn_unit *bswap64_addr;
static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, tcg_insn_unit *target)
{
@@ -614,7 +616,10 @@ static void tcg_out_bswap32u(TCGContext *s, TCGReg ret, TCGReg arg)
tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
tcg_out_dsrl(s, ret, ret, 32);
} else {
- abort();
+ tcg_out_bswap_subr(s, bswap32u_addr);
+ /* delay slot -- never omit the insn, like tcg_out_mov might. */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
+ tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
}
}
@@ -624,7 +629,10 @@ static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg)
tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
tcg_out_opc_reg(s, OPC_DSHD, ret, 0, arg);
} else {
- abort();
+ tcg_out_bswap_subr(s, bswap64_addr);
+ /* delay slot -- never omit the insn, like tcg_out_mov might. */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
+ tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
}
}
@@ -2233,7 +2241,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)
return;
}
- /* Bswap subroutine: Input in TCG_TMP0, output in TCG_TMP3;
+ /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3;
clobbers TCG_TMP1, TCG_TMP2. */
/*
@@ -2259,6 +2267,94 @@ static void tcg_target_qemu_prologue(TCGContext *s)
tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
/* t3 = dcba -- delay slot */
tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
+
+ if (TCG_TARGET_REG_BITS == 32) {
+ return;
+ }
+
+ /*
+ * bswap32u -- unsigned 32-bit swap. a0 = ....abcd.
+ */
+ bswap32u_addr = align_code_ptr(s);
+ /* t1 = (0000)000d */
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff);
+ /* t3 = 000a */
+ tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24);
+ /* t1 = (0000)d000 */
+ tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
+ /* t2 = 00c0 */
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
+ /* t3 = d00a */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
+ /* t1 = 0abc */
+ tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
+ /* t2 = 0c00 */
+ tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
+ /* t1 = 00b0 */
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
+ /* t3 = dc0a */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
+ tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
+ /* t3 = dcba -- delay slot */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
+
+ /*
+ * bswap64 -- 64-bit swap. a0 = abcdefgh
+ */
+ bswap64_addr = align_code_ptr(s);
+ /* t3 = h0000000 */
+ tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56);
+ /* t1 = 0000000a */
+ tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56);
+
+ /* t2 = 000000g0 */
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
+ /* t3 = h000000a */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
+ /* t1 = 00000abc */
+ tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40);
+ /* t2 = 0g000000 */
+ tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
+ /* t1 = 000000b0 */
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
+
+ /* t3 = hg00000a */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
+ /* t2 = 0000abcd */
+ tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32);
+ /* t3 = hg0000ba */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
+
+ /* t1 = 000000c0 */
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00);
+ /* t2 = 0000000d */
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff);
+ /* t1 = 00000c00 */
+ tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8);
+ /* t2 = 0000d000 */
+ tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24);
+
+ /* t3 = hg000cba */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
+ /* t1 = 00abcdef */
+ tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16);
+ /* t3 = hg00dcba */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
+
+ /* t2 = 0000000f */
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff);
+ /* t1 = 000000e0 */
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
+ /* t2 = 00f00000 */
+ tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
+ /* t1 = 000e0000 */
+ tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
+
+ /* t3 = hgf0dcba */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
+ tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
+ /* t3 = hgfedcba -- delay slot */
+ tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
}
static void tcg_target_init(TCGContext *s)
--
2.5.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH v2 06/16] tcg-mips: Adjust move functions for mips64
2016-02-15 3:42 [Qemu-devel] [PATCH v2 00/16] tcg mips64 and mips r6 improvements Richard Henderson
` (4 preceding siblings ...)
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 05/16] tcg-mips: Add bswap32u and bswap64 Richard Henderson
@ 2016-02-15 3:42 ` Richard Henderson
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 07/16] tcg-mips: Adjust load/store " Richard Henderson
` (11 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Richard Henderson @ 2016-02-15 3:42 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, aurelien
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/mips/tcg-target.c | 34 +++++++++++++++++++++++++---------
1 file changed, 25 insertions(+), 9 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 88c032c..0451acb 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -536,23 +536,39 @@ static inline void tcg_out_mov(TCGContext *s, TCGType type,
{
/* Simple reg-reg move, optimising out the 'do nothing' case */
if (ret != arg) {
- tcg_out_opc_reg(s, OPC_ADDU, ret, arg, TCG_REG_ZERO);
+ tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO);
}
}
-static inline void tcg_out_movi(TCGContext *s, TCGType type,
- TCGReg reg, tcg_target_long arg)
+static void tcg_out_movi(TCGContext *s, TCGType type,
+ TCGReg ret, tcg_target_long arg)
{
+ if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
+ arg = (int32_t)arg;
+ }
if (arg == (int16_t)arg) {
- tcg_out_opc_imm(s, OPC_ADDIU, reg, TCG_REG_ZERO, arg);
- } else if (arg == (uint16_t)arg) {
- tcg_out_opc_imm(s, OPC_ORI, reg, TCG_REG_ZERO, arg);
+ tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg);
+ return;
+ }
+ if (arg == (uint16_t)arg) {
+ tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg);
+ return;
+ }
+ if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
+ tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
} else {
- tcg_out_opc_imm(s, OPC_LUI, reg, TCG_REG_ZERO, arg >> 16);
- if (arg & 0xffff) {
- tcg_out_opc_imm(s, OPC_ORI, reg, reg, arg & 0xffff);
+ tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1);
+ if (arg & 0xffff0000ull) {
+ tcg_out_dsll(s, ret, ret, 16);
+ tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16);
+ tcg_out_dsll(s, ret, ret, 16);
+ } else {
+ tcg_out_dsll(s, ret, ret, 32);
}
}
+ if (arg & 0xffff) {
+ tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
+ }
}
static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg)
--
2.5.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH v2 07/16] tcg-mips: Adjust load/store functions for mips64
2016-02-15 3:42 [Qemu-devel] [PATCH v2 00/16] tcg mips64 and mips r6 improvements Richard Henderson
` (5 preceding siblings ...)
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 06/16] tcg-mips: Adjust move functions for mips64 Richard Henderson
@ 2016-02-15 3:42 ` Richard Henderson
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 08/16] tcg-mips: Adjust prologue " Richard Henderson
` (10 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Richard Henderson @ 2016-02-15 3:42 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, aurelien
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/mips/tcg-target.c | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 0451acb..d1266ef 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -689,7 +689,7 @@ static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
if (ofs != lo) {
tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo);
if (addr != TCG_REG_ZERO) {
- tcg_out_opc_reg(s, OPC_ADDU, TCG_TMP0, TCG_TMP0, addr);
+ tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr);
}
addr = TCG_TMP0;
}
@@ -699,13 +699,21 @@ static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
TCGReg arg1, intptr_t arg2)
{
- tcg_out_ldst(s, OPC_LW, arg, arg1, arg2);
+ MIPSInsn opc = OPC_LD;
+ if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
+ opc = OPC_LW;
+ }
+ tcg_out_ldst(s, opc, arg, arg1, arg2);
}
static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
TCGReg arg1, intptr_t arg2)
{
- tcg_out_ldst(s, OPC_SW, arg, arg1, arg2);
+ MIPSInsn opc = OPC_SD;
+ if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
+ opc = OPC_SW;
+ }
+ tcg_out_ldst(s, opc, arg, arg1, arg2);
}
static inline void tcg_out_addi(TCGContext *s, TCGReg reg, TCGArg val)
--
2.5.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH v2 08/16] tcg-mips: Adjust prologue for mips64
2016-02-15 3:42 [Qemu-devel] [PATCH v2 00/16] tcg mips64 and mips r6 improvements Richard Henderson
` (6 preceding siblings ...)
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 07/16] tcg-mips: Adjust load/store " Richard Henderson
@ 2016-02-15 3:42 ` Richard Henderson
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 09/16] tcg-mips: Add tcg unwind info Richard Henderson
` (9 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Richard Henderson @ 2016-02-15 3:42 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, aurelien
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/mips/tcg-target.c | 56 ++++++++++++++++++++++++---------------------------
1 file changed, 26 insertions(+), 30 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index d1266ef..4a3f11a 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -716,16 +716,6 @@ static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
tcg_out_ldst(s, opc, arg, arg1, arg2);
}
-static inline void tcg_out_addi(TCGContext *s, TCGReg reg, TCGArg val)
-{
- if (val == (int16_t)val) {
- tcg_out_opc_imm(s, OPC_ADDIU, reg, reg, val);
- } else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, val);
- tcg_out_opc_reg(s, OPC_ADDU, reg, reg, TCG_TMP0);
- }
-}
-
static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al,
TCGReg ah, TCGArg bl, TCGArg bh, bool cbl,
bool cbh, bool is_sub)
@@ -2224,42 +2214,48 @@ static tcg_insn_unit *align_code_ptr(TCGContext *s)
return s->code_ptr;
}
+/* Stack frame parameters. */
+#define REG_SIZE (TCG_TARGET_REG_BITS / 8)
+#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
+#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
+
+#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
+ + TCG_TARGET_STACK_ALIGN - 1) \
+ & -TCG_TARGET_STACK_ALIGN)
+#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
+
+/* We're expecting to be able to use an immediate for frame allocation. */
+QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff);
+
/* Generate global QEMU prologue and epilogue code */
static void tcg_target_qemu_prologue(TCGContext *s)
{
- int i, frame_size;
-
- /* reserve some stack space, also for TCG temps. */
- frame_size = ARRAY_SIZE(tcg_target_callee_save_regs) * 4
- + TCG_STATIC_CALL_ARGS_SIZE
- + CPU_TEMP_BUF_NLONGS * sizeof(long);
- frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
- ~(TCG_TARGET_STACK_ALIGN - 1);
- tcg_set_frame(s, TCG_REG_SP, ARRAY_SIZE(tcg_target_callee_save_regs) * 4
- + TCG_STATIC_CALL_ARGS_SIZE,
- CPU_TEMP_BUF_NLONGS * sizeof(long));
+ int i;
+
+ tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
/* TB prologue */
- tcg_out_addi(s, TCG_REG_SP, -frame_size);
- for(i = 0 ; i < ARRAY_SIZE(tcg_target_callee_save_regs) ; i++) {
- tcg_out_st(s, TCG_TYPE_I32, tcg_target_callee_save_regs[i],
- TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE + i * 4);
+ tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
+ for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
+ tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
+ TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
}
/* Call generated code */
tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
+ /* delay slot */
tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
- tb_ret_addr = s->code_ptr;
/* TB epilogue */
- for(i = 0 ; i < ARRAY_SIZE(tcg_target_callee_save_regs) ; i++) {
- tcg_out_ld(s, TCG_TYPE_I32, tcg_target_callee_save_regs[i],
- TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE + i * 4);
+ tb_ret_addr = s->code_ptr;
+ for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
+ tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
+ TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
}
tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
/* delay slot */
- tcg_out_addi(s, TCG_REG_SP, frame_size);
+ tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
if (use_mips32r2_instructions) {
return;
--
2.5.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH v2 09/16] tcg-mips: Add tcg unwind info
2016-02-15 3:42 [Qemu-devel] [PATCH v2 00/16] tcg mips64 and mips r6 improvements Richard Henderson
` (7 preceding siblings ...)
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 08/16] tcg-mips: Adjust prologue " Richard Henderson
@ 2016-02-15 3:42 ` Richard Henderson
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 10/16] tcg-mips: Adjust qemu_ld/st for mips64 Richard Henderson
` (8 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Richard Henderson @ 2016-02-15 3:42 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, aurelien
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/mips/tcg-target.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 4a3f11a..25b079b 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -2420,3 +2420,47 @@ void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
*ptr = deposit32(*ptr, 0, 26, addr >> 2);
flush_icache_range(jmp_addr, jmp_addr + 4);
}
+
+typedef struct {
+ DebugFrameHeader h;
+ uint8_t fde_def_cfa[4];
+ uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
+} DebugFrame;
+
+#define ELF_HOST_MACHINE EM_MIPS
+/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS,
+ which is good because they're really quite complicated for MIPS. */
+
+static const DebugFrame debug_frame = {
+ .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
+ .h.cie.id = -1,
+ .h.cie.version = 1,
+ .h.cie.code_align = 1,
+ .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
+ .h.cie.return_column = TCG_REG_RA,
+
+ /* Total FDE size does not include the "len" member. */
+ .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
+
+ .fde_def_cfa = {
+ 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
+ (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
+ (FRAME_SIZE >> 7)
+ },
+ .fde_reg_ofs = {
+ 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */
+ 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */
+ 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */
+ 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */
+ 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */
+ 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */
+ 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */
+ 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */
+ 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */
+ }
+};
+
+void tcg_register_jit(void *buf, size_t buf_size)
+{
+ tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
+}
--
2.5.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH v2 10/16] tcg-mips: Adjust qemu_ld/st for mips64
2016-02-15 3:42 [Qemu-devel] [PATCH v2 00/16] tcg mips64 and mips r6 improvements Richard Henderson
` (8 preceding siblings ...)
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 09/16] tcg-mips: Add tcg unwind info Richard Henderson
@ 2016-02-15 3:42 ` Richard Henderson
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 11/16] tcg-mips: Adjust calling conventions " Richard Henderson
` (7 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Richard Henderson @ 2016-02-15 3:42 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, aurelien
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/mips/tcg-target.c | 188 ++++++++++++++++++++++++++++++++++----------------
1 file changed, 130 insertions(+), 58 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 25b079b..f61d6c7 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -33,8 +33,14 @@
# define MIPS_BE 0
#endif
-#define LO_OFF (MIPS_BE * 4)
-#define HI_OFF (4 - LO_OFF)
+#if TCG_TARGET_REG_BITS == 32
+# define LO_OFF (MIPS_BE * 4)
+# define HI_OFF (4 - LO_OFF)
+#else
+extern int link_error(void);
+# define LO_OFF link_error()
+# define HI_OFF link_error()
+#endif
#ifndef NDEBUG
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
@@ -188,7 +194,7 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
tcg_regset_set(ct->u.regs, 0xffffffff);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
#if defined(CONFIG_SOFTMMU)
- if (TARGET_LONG_BITS == 64) {
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
}
#endif
@@ -198,11 +204,11 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
tcg_regset_set(ct->u.regs, 0xffffffff);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
#if defined(CONFIG_SOFTMMU)
- if (TARGET_LONG_BITS == 32) {
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1);
- } else {
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3);
+ } else {
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1);
}
#endif
break;
@@ -1080,6 +1086,10 @@ static void * const qemu_ld_helpers[16] = {
[MO_BESW] = helper_be_ldsw_mmu,
[MO_BEUL] = helper_be_ldul_mmu,
[MO_BEQ] = helper_be_ldq_mmu,
+#if TCG_TARGET_REG_BITS == 64
+ [MO_LESL] = helper_le_ldsl_mmu,
+ [MO_BESL] = helper_be_ldsl_mmu,
+#endif
};
static void * const qemu_st_helpers[16] = {
@@ -1107,6 +1117,9 @@ static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg)
if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg);
} else {
+ /* For N32 and N64, the initial offset is different. But there
+ we also have 8 argument register so we don't run out here. */
+ tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i);
}
return i + 1;
@@ -1148,6 +1161,7 @@ static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg)
static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah)
{
+ tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
i = (i + 1) & ~1;
i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al));
i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah));
@@ -1161,6 +1175,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
tcg_insn_unit *label_ptr[2], bool is_load)
{
TCGMemOp s_bits = get_memop(oi) & MO_SIZE;
+ target_ulong mask = TARGET_PAGE_MASK | ((1 << s_bits) - 1);
int mem_index = get_mmuidx(oi);
int cmp_off
= (is_load
@@ -1168,11 +1183,11 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
: offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
- tcg_out_opc_sa(s, OPC_SRL, TCG_REG_A0, addrl,
+ tcg_out_opc_sa(s, ALIAS_TSRL, TCG_REG_A0, addrl,
TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_A0, TCG_REG_A0,
(CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
- tcg_out_opc_reg(s, OPC_ADDU, TCG_REG_A0, TCG_REG_A0, TCG_AREG0);
+ tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, TCG_REG_A0, TCG_AREG0);
/* Compensate for very large offsets. */
if (add_off >= 0x8000) {
@@ -1182,43 +1197,48 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
QEMU_BUILD_BUG_ON(offsetof(CPUArchState,
tlb_table[NB_MMU_MODES - 1][1])
> 0x7ff0 + 0x7fff);
- tcg_out_opc_imm(s, OPC_ADDIU, TCG_REG_A0, TCG_REG_A0, 0x7ff0);
+ tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, TCG_REG_A0, 0x7ff0);
cmp_off -= 0x7ff0;
add_off -= 0x7ff0;
}
- /* Load the (low half) tlb comparator. */
- tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, TCG_REG_A0,
- cmp_off + (TARGET_LONG_BITS == 64 ? LO_OFF : 0));
-
- /* Mask the page bits, keeping the alignment bits to compare against.
- In between on 32-bit targets, load the tlb addend for the fast path. */
- tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1,
- TARGET_PAGE_MASK | ((1 << s_bits) - 1));
- if (TARGET_LONG_BITS == 32) {
- tcg_out_opc_imm(s, OPC_LW, TCG_REG_A0, TCG_REG_A0, add_off);
+ /* Load the (low half) tlb comparator. Mask the page bits, keeping the
+ alignment bits to compare against. */
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
+ tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_REG_A0, cmp_off + LO_OFF);
+ tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, mask);
+ } else {
+ tcg_out_ld(s, TCG_TYPE_TL, TCG_TMP0, TCG_REG_A0, cmp_off);
+ tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, mask);
+ /* No second compare is required here;
+ load the tlb addend for the fast path. */
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_REG_A0, add_off);
}
tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl);
+ /* Zero extend a 32-bit guest address for a 64-bit host. */
+ if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+ tcg_out_ext32u(s, base, addrl);
+ addrl = base;
+ }
+
label_ptr[0] = s->code_ptr;
tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
/* Load and test the high half tlb comparator. */
- if (TARGET_LONG_BITS == 64) {
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
/* delay slot */
- tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, TCG_REG_A0, cmp_off + HI_OFF);
+ tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_REG_A0, cmp_off + HI_OFF);
- /* Load the tlb addend for the fast path. We can't do it earlier with
- 64-bit targets or we'll clobber a0 before reading the high half tlb
- comparator. */
- tcg_out_opc_imm(s, OPC_LW, TCG_REG_A0, TCG_REG_A0, add_off);
+ /* Load the tlb addend for the fast path. */
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_REG_A0, add_off);
label_ptr[1] = s->code_ptr;
tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0);
}
/* delay slot */
- tcg_out_opc_reg(s, OPC_ADDU, base, TCG_REG_A0, addrl);
+ tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_REG_A0, addrl);
}
static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
@@ -1236,7 +1256,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
label->addrhi_reg = addrhi;
label->raddr = raddr;
label->label_ptr[0] = label_ptr[0];
- if (TARGET_LONG_BITS == 64) {
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
label->label_ptr[1] = label_ptr[1];
}
}
@@ -1250,12 +1270,12 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
/* resolve label address */
reloc_pc16(l->label_ptr[0], s->code_ptr);
- if (TARGET_LONG_BITS == 64) {
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
reloc_pc16(l->label_ptr[1], s->code_ptr);
}
i = 1;
- if (TARGET_LONG_BITS == 64) {
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
} else {
i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
@@ -1267,7 +1287,7 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
v0 = l->datalo_reg;
- if ((opc & MO_SIZE) == MO_64) {
+ if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
/* We eliminated V0 from the possible output registers, so it
cannot be clobbered here. So we must move V1 first. */
if (MIPS_BE) {
@@ -1293,12 +1313,12 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
/* resolve label address */
reloc_pc16(l->label_ptr[0], s->code_ptr);
- if (TARGET_LONG_BITS == 64) {
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
reloc_pc16(l->label_ptr[1], s->code_ptr);
}
i = 1;
- if (TARGET_LONG_BITS == 64) {
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg);
} else {
i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg);
@@ -1310,14 +1330,15 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
case MO_16:
i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg);
break;
- case MO_32:
- i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
- break;
case MO_64:
- i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg);
- break;
+ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
+ i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg);
+ break;
+ }
+ /* FALLTHRU */
default:
- tcg_abort();
+ i = tcg_out_call_iarg_reg(s, i, l->datalo_reg);
+ break;
}
i = tcg_out_call_iarg_imm(s, i, oi);
@@ -1332,7 +1353,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
#endif
static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
- TCGReg base, TCGMemOp opc)
+ TCGReg base, TCGMemOp opc, bool is_64)
{
switch (opc & (MO_SSIZE | MO_BSWAP)) {
case MO_UB:
@@ -1341,6 +1362,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
case MO_SB:
tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
break;
+
case MO_UW | MO_BSWAP:
tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
tcg_out_bswap16(s, lo, TCG_TMP1);
@@ -1348,6 +1370,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
case MO_UW:
tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
break;
+
case MO_SW | MO_BSWAP:
tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
tcg_out_bswap16s(s, lo, TCG_TMP1);
@@ -1355,7 +1378,22 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
case MO_SW:
tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
break;
+
case MO_UL | MO_BSWAP:
+ if (TCG_TARGET_REG_BITS == 64 && is_64) {
+ if (use_mips32r2_instructions) {
+ tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
+ tcg_out_bswap32u(s, lo, lo);
+ } else {
+ tcg_out_bswap_subr(s, bswap32u_addr);
+ /* delay slot */
+ tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0);
+ tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
+ }
+ break;
+ }
+ /* FALLTHRU */
+ case MO_SL | MO_BSWAP:
if (use_mips32r2_instructions) {
tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
tcg_out_bswap32(s, lo, lo);
@@ -1366,11 +1404,29 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3);
}
break;
+
case MO_UL:
+ if (TCG_TARGET_REG_BITS == 64 && is_64) {
+ tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
+ break;
+ }
+ /* FALLTHRU */
+ case MO_SL:
tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
break;
+
case MO_Q | MO_BSWAP:
- if (use_mips32r2_instructions) {
+ if (TCG_TARGET_REG_BITS == 64) {
+ if (use_mips32r2_instructions) {
+ tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
+ tcg_out_bswap64(s, lo, lo);
+ } else {
+ tcg_out_bswap_subr(s, bswap64_addr);
+ /* delay slot */
+ tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0);
+ tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3);
+ }
+ } else if (use_mips32r2_instructions) {
tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0);
tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4);
tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0);
@@ -1390,7 +1446,9 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
break;
case MO_Q:
/* Prefer to load from offset 0 first, but allow for overlap. */
- if (MIPS_BE ? hi != base : lo == base) {
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
+ } else if (MIPS_BE ? hi != base : lo == base) {
tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
} else {
@@ -1415,27 +1473,31 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
TCGReg base = TCG_REG_A0;
data_regl = *args++;
- data_regh = (is_64 ? *args++ : 0);
+ data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
addr_regl = *args++;
- addr_regh = (TARGET_LONG_BITS == 64 ? *args++ : 0);
+ addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
oi = *args++;
opc = get_memop(oi);
#if defined(CONFIG_SOFTMMU)
tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1);
- tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc);
+ tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
add_qemu_ldst_label(s, 1, oi, data_regl, data_regh, addr_regl, addr_regh,
s->code_ptr, label_ptr);
#else
+ if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+ tcg_out_ext32u(s, base, addr_regl);
+ addr_regl = base;
+ }
if (guest_base == 0 && data_regl != addr_regl) {
base = addr_regl;
} else if (guest_base == (int16_t)guest_base) {
- tcg_out_opc_imm(s, OPC_ADDIU, base, addr_regl, guest_base);
+ tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
} else {
tcg_out_movi(s, TCG_TYPE_PTR, base, guest_base);
- tcg_out_opc_reg(s, OPC_ADDU, base, base, addr_regl);
+ tcg_out_opc_reg(s, ALIAS_PADD, base, base, addr_regl);
}
- tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc);
+ tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
#endif
}
@@ -1470,7 +1532,10 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
break;
case MO_64 | MO_BSWAP:
- if (use_mips32r2_instructions) {
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_out_bswap64(s, TCG_TMP3, lo);
+ tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0);
+ } else if (use_mips32r2_instructions) {
tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi);
tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo);
tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16);
@@ -1485,8 +1550,12 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
}
break;
case MO_64:
- tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0);
- tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4);
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_out_opc_imm(s, OPC_SD, lo, base, 0);
+ } else {
+ tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0);
+ tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4);
+ }
break;
default:
@@ -1506,9 +1575,9 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
TCGReg base = TCG_REG_A0;
data_regl = *args++;
- data_regh = (is_64 ? *args++ : 0);
+ data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
addr_regl = *args++;
- addr_regh = (TARGET_LONG_BITS == 64 ? *args++ : 0);
+ addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
oi = *args++;
opc = get_memop(oi);
@@ -1518,15 +1587,18 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
add_qemu_ldst_label(s, 0, oi, data_regl, data_regh, addr_regl, addr_regh,
s->code_ptr, label_ptr);
#else
+ base = TCG_REG_A0;
+ if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+ tcg_out_ext32u(s, base, addr_regl);
+ addr_regl = base;
+ }
if (guest_base == 0) {
base = addr_regl;
+ } else if (guest_base == (int16_t)guest_base) {
+ tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
} else {
- if (guest_base == (int16_t)guest_base) {
- tcg_out_opc_imm(s, OPC_ADDIU, base, addr_regl, guest_base);
- } else {
- tcg_out_movi(s, TCG_TYPE_PTR, base, guest_base);
- tcg_out_opc_reg(s, OPC_ADDU, base, base, addr_regl);
- }
+ tcg_out_movi(s, TCG_TYPE_PTR, base, guest_base);
+ tcg_out_opc_reg(s, ALIAS_PADD, base, base, addr_regl);
}
tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
#endif
--
2.5.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH v2 11/16] tcg-mips: Adjust calling conventions for mips64
2016-02-15 3:42 [Qemu-devel] [PATCH v2 00/16] tcg mips64 and mips r6 improvements Richard Henderson
` (9 preceding siblings ...)
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 10/16] tcg-mips: Adjust qemu_ld/st for mips64 Richard Henderson
@ 2016-02-15 3:42 ` Richard Henderson
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 12/16] tcg-mips: Improve tcg_out_movi " Richard Henderson
` (6 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Richard Henderson @ 2016-02-15 3:42 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, aurelien
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/mips/tcg-target.c | 21 +++++++++++++++------
tcg/mips/tcg-target.h | 19 +++++++++++++++----
2 files changed, 30 insertions(+), 10 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index f61d6c7..8fb2ab0 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -98,10 +98,6 @@ static const TCGReg tcg_target_reg_alloc_order[] = {
TCG_REG_S8,
/* Call clobbered registers. */
- TCG_REG_T0,
- TCG_REG_T1,
- TCG_REG_T2,
- TCG_REG_T3,
TCG_REG_T4,
TCG_REG_T5,
TCG_REG_T6,
@@ -112,17 +108,27 @@ static const TCGReg tcg_target_reg_alloc_order[] = {
TCG_REG_V0,
/* Argument registers, opposite order of allocation. */
+ TCG_REG_T3,
+ TCG_REG_T2,
+ TCG_REG_T1,
+ TCG_REG_T0,
TCG_REG_A3,
TCG_REG_A2,
TCG_REG_A1,
TCG_REG_A0,
};
-static const TCGReg tcg_target_call_iarg_regs[4] = {
+static const TCGReg tcg_target_call_iarg_regs[] = {
TCG_REG_A0,
TCG_REG_A1,
TCG_REG_A2,
- TCG_REG_A3
+ TCG_REG_A3,
+#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
+ TCG_REG_T0,
+ TCG_REG_T1,
+ TCG_REG_T2,
+ TCG_REG_T3,
+#endif
};
static const TCGReg tcg_target_call_oarg_regs[2] = {
@@ -2453,6 +2459,9 @@ static void tcg_target_init(TCGContext *s)
{
tcg_target_detect_isa();
tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32], 0xffffffff);
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I64], 0xffffffff);
+ }
tcg_regset_set(tcg_target_call_clobber_regs,
(1 << TCG_REG_V0) |
(1 << TCG_REG_V1) |
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index 1a9e54c..3eb771f 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -26,7 +26,14 @@
#ifndef TCG_TARGET_MIPS
#define TCG_TARGET_MIPS 1
-#define TCG_TARGET_REG_BITS 32
+#if _MIPS_SIM == _ABIO32
+# define TCG_TARGET_REG_BITS 32
+#elif _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
+# define TCG_TARGET_REG_BITS 64
+#else
+# error "Unknown ABI"
+#endif
+
#define TCG_TARGET_INSN_UNIT_SIZE 4
#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
#define TCG_TARGET_NB_REGS 32
@@ -70,9 +77,13 @@ typedef enum {
} TCGReg;
/* used for function call generation */
-#define TCG_TARGET_STACK_ALIGN 8
-#define TCG_TARGET_CALL_STACK_OFFSET 16
-#define TCG_TARGET_CALL_ALIGN_ARGS 1
+#define TCG_TARGET_STACK_ALIGN 16
+#if _MIPS_SIM == _ABIO32
+# define TCG_TARGET_CALL_STACK_OFFSET 16
+#else
+# define TCG_TARGET_CALL_STACK_OFFSET 0
+#endif
+#define TCG_TARGET_CALL_ALIGN_ARGS 1
/* MOVN/MOVZ instructions detection */
#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \
--
2.5.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH v2 12/16] tcg-mips: Improve tcg_out_movi for mips64
2016-02-15 3:42 [Qemu-devel] [PATCH v2 00/16] tcg mips64 and mips r6 improvements Richard Henderson
` (10 preceding siblings ...)
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 11/16] tcg-mips: Adjust calling conventions " Richard Henderson
@ 2016-02-15 3:42 ` Richard Henderson
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 13/16] tcg-mips: Use mips64r6 instructions in tcg_out_ldst Richard Henderson
` (5 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Richard Henderson @ 2016-02-15 3:42 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, aurelien
For r6, the ADDIUPC, ALUIPC, DAHI and DATI instructions can eliminate 2-4
insns off the pre-r6 full 64-bit immediate load sequence.
For pre-r6, NAL can do the same for the special, but common, case of the
return address for the qemu_ld/st slow paths.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/mips/tcg-target.c | 117 ++++++++++++++++++++++++++++++++++++++++++++++----
1 file changed, 109 insertions(+), 8 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 8fb2ab0..b4239cb 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -282,7 +282,9 @@ typedef enum {
OPC_ORI = 015 << 26,
OPC_XORI = 016 << 26,
OPC_LUI = 017 << 26,
+ OPC_AUI = OPC_LUI,
OPC_DADDIU = 031 << 26,
+ OPC_DAUI = 035 << 26,
OPC_LB = 040 << 26,
OPC_LH = 041 << 26,
OPC_LW = 043 << 26,
@@ -362,6 +364,9 @@ typedef enum {
OPC_REGIMM = 001 << 26,
OPC_BLTZ = OPC_REGIMM | (000 << 16),
OPC_BGEZ = OPC_REGIMM | (001 << 16),
+ OPC_DAHI = OPC_REGIMM | (006 << 16),
+ OPC_NAL = OPC_REGIMM | (020 << 16) | 1, /* bltzal zero, .+8 */
+ OPC_DATI = OPC_REGIMM | (036 << 16),
OPC_SPECIAL2 = 034 << 26,
OPC_MUL_R5 = OPC_SPECIAL2 | 002,
@@ -381,6 +386,10 @@ typedef enum {
OPC_SEB = OPC_SPECIAL3 | 02040,
OPC_SEH = OPC_SPECIAL3 | 03040,
+ OPC_PCREL = 073 << 26,
+ OPC_ADDIUPC = OPC_PCREL | (0 << 19),
+ OPC_ALUIPC = OPC_PCREL | (3 << 19) | (7 << 16),
+
/* MIPS r6 doesn't have JR, JALR should be used instead */
OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5,
@@ -427,6 +436,17 @@ static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc,
tcg_out32(s, inst);
}
+static inline void tcg_out_opc_pc19(TCGContext *s, MIPSInsn opc,
+ TCGReg rs, TCGArg imm)
+{
+ int32_t inst;
+
+ inst = opc;
+ inst |= (rs & 0x1F) << 21;
+ inst |= (imm & 0x7ffff);
+ tcg_out32(s, inst);
+}
+
/*
* Type bitfield
*/
@@ -555,6 +575,9 @@ static inline void tcg_out_mov(TCGContext *s, TCGType type,
static void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg ret, tcg_target_long arg)
{
+ uintptr_t pc = (uintptr_t)s->code_ptr;
+ intptr_t disp;
+
if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
arg = (int32_t)arg;
}
@@ -566,18 +589,96 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg);
return;
}
+
+ /* PC-relative address load, part 1. The out-of-line slow paths
+ of qemu_ld/st compute the "return address" of the in-line fast
+ path, so that we can find the guest instruction that triggered
+ the memory fault. Here, we can do that in one instruction. */
+ if (use_mips32r6_instructions && (arg & 3) == 0) {
+ disp = arg - pc;
+ if (disp == sextract32(disp, 0, 21)) {
+ tcg_out_opc_pc19(s, OPC_ADDIUPC, ret, disp >> 2);
+ return;
+ }
+ }
+
if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
- } else {
- tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1);
- if (arg & 0xffff0000ull) {
- tcg_out_dsll(s, ret, ret, 16);
- tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16);
- tcg_out_dsll(s, ret, ret, 16);
- } else {
- tcg_out_dsll(s, ret, ret, 32);
+ goto do_lo16;
+ }
+
+ if (use_mips32r6_instructions) {
+ tcg_target_long tmp;
+ TCGReg in;
+
+ /* PC-relative address load, part 2. Here we are able to compute
+ a +- 2GB relative address in two instructions. This not likely
+ to be within code_gen_buffer, but a helper function address or
+ other host memory that just happens to be in range. */
+ disp = sextract64(arg, 16, 48) - sextract64(pc, 16, 48);
+ if (disp == (int16_t)disp) {
+ tcg_out_opc_imm(s, OPC_ALUIPC, 0, ret, disp);
+ goto do_lo16;
+ }
+
+ /* The R6 manual recommends construction of immediates in
+ order of low to high (ADDI, AUI, DAHI, DATI) in order
+ to simplify hardware recognizing these sequences. */
+
+ in = TCG_REG_ZERO;
+ tmp = (int16_t)arg;
+ if (tmp) {
+ tcg_out_opc_imm(s, OPC_ADDIU, ret, in, tmp);
+ in = ret;
}
+ arg = (arg - tmp) >> 16;
+ tmp = (int16_t)arg;
+
+ /* Note that DAHI and DATI only have one register operand,
+ and are thus we must put a zero low part in place. Also
+ note that we already eliminated simple 32-bit constants
+ so we know this must happen. */
+ if (tmp || in != ret) {
+ tcg_out_opc_imm(s, OPC_AUI, ret, in, tmp);
+ }
+ arg = (arg - tmp) >> 16;
+ tmp = (int16_t)arg;
+
+ if (tmp) {
+ tcg_out_opc_imm(s, OPC_DAHI, 0, ret, tmp);
+ }
+ arg = (arg - tmp) >> 16;
+ tcg_debug_assert(arg == (int16_t)arg);
+
+ if (arg) {
+ tcg_out_opc_imm(s, OPC_DATI, 0, ret, arg);
+ }
+ return;
+ }
+
+ /* PC-relative address load, part 3. For mips64 pre-r6, we can use
+ NAL (nop and link, aka BLTZAL with a false condition) to load the
+ return address register with pc+8. This lets us compute the
+ return address for qemu_ld/st only in 2 insns. */
+ disp = arg - (pc + 8);
+ if (disp == (int16_t)disp) {
+ tcg_out32(s, OPC_NAL);
+ tcg_out_opc_imm(s, OPC_DADDIU, ret, TCG_REG_RA, disp);
+ return;
+ }
+
+ /* Last resort: To build a full 64-bit constant, we load the high
+ 32 bits, then shift and or in the low 32 bits. This may take
+ up to 6 instructions. */
+ tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1);
+ if (arg & 0xffff0000ull) {
+ tcg_out_dsll(s, ret, ret, 16);
+ tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16);
+ tcg_out_dsll(s, ret, ret, 16);
+ } else {
+ tcg_out_dsll(s, ret, ret, 32);
}
+ do_lo16:
if (arg & 0xffff) {
tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
}
--
2.5.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH v2 13/16] tcg-mips: Use mips64r6 instructions in tcg_out_ldst
2016-02-15 3:42 [Qemu-devel] [PATCH v2 00/16] tcg mips64 and mips r6 improvements Richard Henderson
` (11 preceding siblings ...)
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 12/16] tcg-mips: Improve tcg_out_movi " Richard Henderson
@ 2016-02-15 3:42 ` Richard Henderson
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 14/16] tcg-mips: Use mips64r6 instructions in constant addition Richard Henderson
` (4 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Richard Henderson @ 2016-02-15 3:42 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, aurelien
The DAUI, DAHI, and DATI insns can be used to eliminate
one extra instruction in these cases.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/mips/tcg-target.c | 40 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index b4239cb..52e1edc 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -402,6 +402,7 @@ typedef enum {
/* Aliases for convenience. */
ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU,
ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU,
+ ALIAS_PAUI = sizeof(void *) == 4 ? OPC_AUI : OPC_DAUI,
ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32
? OPC_SRL : OPC_DSRL,
} MIPSInsn;
@@ -795,9 +796,48 @@ static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
}
}
+static void tcg_out_r6_ofs(TCGContext *s, MIPSInsn opl, MIPSInsn oph,
+ TCGReg reg0, TCGReg reg1, tcg_target_long ofs)
+{
+ TCGReg scratch = TCG_TMP0;
+ int16_t lo = ofs;
+ int32_t hi = ofs - lo;
+
+ ofs = ofs - hi - lo;
+ if (oph == OPC_DAUI && ofs != 0) {
+ tcg_target_long tmp;
+
+ /* Bits are set in the high 32-bit half. Thus we require the
+ use of DAHI and/or DATI. The R6 manual recommends addition
+ of immediates in order of mid to high (DAUI, DAHI, DATI, OPL)
+ in order to simplify hardware recognizing these sequences. */
+
+ tcg_out_opc_imm(s, OPC_DAUI, scratch, reg1, hi >> 16);
+
+ tmp = ofs >> 16 >> 16;
+ if (tmp & 0xffff) {
+ tcg_out_opc_imm(s, OPC_DAHI, 0, scratch, tmp);
+ }
+ tmp = (tmp - (int16_t)tmp) >> 16;
+ if (tmp) {
+ tcg_out_opc_imm(s, OPC_DATI, 0, scratch, tmp);
+ }
+ reg1 = scratch;
+ } else if (hi != 0) {
+ tcg_out_opc_imm(s, oph, scratch, reg1, hi >> 16);
+ reg1 = scratch;
+ }
+ tcg_out_opc_imm(s, opc, reg0, reg1, lo);
+}
+
static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
TCGReg addr, intptr_t ofs)
{
+ if (use_mips32r6_instructions) {
+ tcg_out_r6_ofs(s, opc, ALIAS_PAUI, data, addr, ofs);
+ return;
+ }
+
int16_t lo = ofs;
if (ofs != lo) {
tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo);
--
2.5.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH v2 14/16] tcg-mips: Use mips64r6 instructions in constant addition
2016-02-15 3:42 [Qemu-devel] [PATCH v2 00/16] tcg mips64 and mips r6 improvements Richard Henderson
` (12 preceding siblings ...)
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 13/16] tcg-mips: Use mips64r6 instructions in tcg_out_ldst Richard Henderson
@ 2016-02-15 3:42 ` Richard Henderson
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 15/16] tcg-mips: Use mipsr6 instructions in branches Richard Henderson
` (3 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Richard Henderson @ 2016-02-15 3:42 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, aurelien
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/mips/tcg-target.c | 59 ++++++++++++++++++++++++++++++++++++++++++---------
1 file changed, 49 insertions(+), 10 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 52e1edc..ab72715 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -221,12 +221,26 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
case 'I':
ct->ct |= TCG_CT_CONST_U16;
break;
+ case 'a':
+ /* mips r6 can add any constant without needing a temporary. */
+ if (use_mips32r6_instructions) {
+ ct->ct |= TCG_CT_CONST;
+ break;
+ }
+ /* fallthru */
case 'J':
ct->ct |= TCG_CT_CONST_S16;
break;
case 'K':
ct->ct |= TCG_CT_CONST_P2M1;
break;
+ case 's':
+ /* mips r6 can subtract any constant without needing a temporary. */
+ if (use_mips32r6_instructions) {
+ ct->ct |= TCG_CT_CONST;
+ break;
+ }
+ /* fallthru */
case 'N':
ct->ct |= TCG_CT_CONST_N16;
break;
@@ -797,9 +811,10 @@ static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
}
static void tcg_out_r6_ofs(TCGContext *s, MIPSInsn opl, MIPSInsn oph,
- TCGReg reg0, TCGReg reg1, tcg_target_long ofs)
+ TCGReg reg0, TCGReg reg1,
+ tcg_target_long ofs, bool is_mem)
{
- TCGReg scratch = TCG_TMP0;
+ TCGReg scratch = is_mem ? TCG_TMP0 : reg0;
int16_t lo = ofs;
int32_t hi = ofs - lo;
@@ -810,9 +825,15 @@ static void tcg_out_r6_ofs(TCGContext *s, MIPSInsn opl, MIPSInsn oph,
/* Bits are set in the high 32-bit half. Thus we require the
use of DAHI and/or DATI. The R6 manual recommends addition
of immediates in order of mid to high (DAUI, DAHI, DATI, OPL)
- in order to simplify hardware recognizing these sequences. */
+ in order to simplify hardware recognizing these sequences.
+ Ignore this wrt DADDIU if it will save one instruction. */
- tcg_out_opc_imm(s, OPC_DAUI, scratch, reg1, hi >> 16);
+ if (hi == 0 && lo != 0 && !is_mem) {
+ tcg_out_opc_imm(s, OPC_DADDIU, scratch, reg1, lo);
+ lo = 0;
+ } else if (hi != 0 || reg1 != scratch) {
+ tcg_out_opc_imm(s, OPC_DAUI, scratch, reg1, hi >> 16);
+ }
tmp = ofs >> 16 >> 16;
if (tmp & 0xffff) {
@@ -827,14 +848,16 @@ static void tcg_out_r6_ofs(TCGContext *s, MIPSInsn opl, MIPSInsn oph,
tcg_out_opc_imm(s, oph, scratch, reg1, hi >> 16);
reg1 = scratch;
}
- tcg_out_opc_imm(s, opc, reg0, reg1, lo);
+ if (is_mem || lo != 0 || reg0 != reg1) {
+ tcg_out_opc_imm(s, opl, reg0, reg1, lo);
+ }
}
static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
TCGReg addr, intptr_t ofs)
{
if (use_mips32r6_instructions) {
- tcg_out_r6_ofs(s, opc, ALIAS_PAUI, data, addr, ofs);
+ tcg_out_r6_ofs(s, opc, ALIAS_PAUI, data, addr, ofs, true);
return;
}
@@ -1846,9 +1869,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_add_i32:
+ if (use_mips32r6_instructions && c2) {
+ tcg_out_r6_ofs(s, OPC_ADDIU, OPC_AUI, a0, a1, (int32_t)a2, false);
+ break;
+ }
i1 = OPC_ADDU, i2 = OPC_ADDIU;
goto do_binary;
case INDEX_op_add_i64:
+ if (use_mips32r6_instructions && c2) {
+ tcg_out_r6_ofs(s, OPC_DADDIU, OPC_DAUI, a0, a1, a2, false);
+ break;
+ }
i1 = OPC_DADDU, i2 = OPC_DADDIU;
goto do_binary;
case INDEX_op_or_i32:
@@ -1868,9 +1899,17 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_sub_i32:
+ if (use_mips32r6_instructions && c2) {
+ tcg_out_r6_ofs(s, OPC_ADDIU, OPC_AUI, a0, a1, (int32_t)-a2, false);
+ break;
+ }
i1 = OPC_SUBU, i2 = OPC_ADDIU;
goto do_subtract;
case INDEX_op_sub_i64:
+ if (use_mips32r6_instructions && c2) {
+ tcg_out_r6_ofs(s, OPC_DADDIU, OPC_DAUI, a0, a1, -a2, false);
+ break;
+ }
i1 = OPC_DSUBU, i2 = OPC_DADDIU;
do_subtract:
if (c2) {
@@ -2202,7 +2241,7 @@ static const TCGTargetOpDef mips_op_defs[] = {
{ INDEX_op_st16_i32, { "rZ", "r" } },
{ INDEX_op_st_i32, { "rZ", "r" } },
- { INDEX_op_add_i32, { "r", "rZ", "rJ" } },
+ { INDEX_op_add_i32, { "r", "rZ", "ra" } },
{ INDEX_op_mul_i32, { "r", "rZ", "rZ" } },
#if !use_mips32r6_instructions
{ INDEX_op_muls2_i32, { "r", "r", "rZ", "rZ" } },
@@ -2214,7 +2253,7 @@ static const TCGTargetOpDef mips_op_defs[] = {
{ INDEX_op_divu_i32, { "r", "rZ", "rZ" } },
{ INDEX_op_rem_i32, { "r", "rZ", "rZ" } },
{ INDEX_op_remu_i32, { "r", "rZ", "rZ" } },
- { INDEX_op_sub_i32, { "r", "rZ", "rN" } },
+ { INDEX_op_sub_i32, { "r", "rZ", "rs" } },
{ INDEX_op_and_i32, { "r", "rZ", "rIK" } },
{ INDEX_op_nor_i32, { "r", "rZ", "rZ" } },
@@ -2264,7 +2303,7 @@ static const TCGTargetOpDef mips_op_defs[] = {
{ INDEX_op_st32_i64, { "rZ", "r" } },
{ INDEX_op_st_i64, { "rZ", "r" } },
- { INDEX_op_add_i64, { "r", "rZ", "rJ" } },
+ { INDEX_op_add_i64, { "r", "rZ", "ra" } },
{ INDEX_op_mul_i64, { "r", "rZ", "rZ" } },
#if !use_mips32r6_instructions
{ INDEX_op_muls2_i64, { "r", "r", "rZ", "rZ" } },
@@ -2276,7 +2315,7 @@ static const TCGTargetOpDef mips_op_defs[] = {
{ INDEX_op_divu_i64, { "r", "rZ", "rZ" } },
{ INDEX_op_rem_i64, { "r", "rZ", "rZ" } },
{ INDEX_op_remu_i64, { "r", "rZ", "rZ" } },
- { INDEX_op_sub_i64, { "r", "rZ", "rN" } },
+ { INDEX_op_sub_i64, { "r", "rZ", "rs" } },
{ INDEX_op_and_i64, { "r", "rZ", "rIK" } },
{ INDEX_op_nor_i64, { "r", "rZ", "rZ" } },
--
2.5.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH v2 15/16] tcg-mips: Use mipsr6 instructions in branches
2016-02-15 3:42 [Qemu-devel] [PATCH v2 00/16] tcg mips64 and mips r6 improvements Richard Henderson
` (13 preceding siblings ...)
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 14/16] tcg-mips: Use mips64r6 instructions in constant addition Richard Henderson
@ 2016-02-15 3:42 ` Richard Henderson
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 16/16] tcg-mips: Use mipsr6 instructions in calls Richard Henderson
` (2 subsequent siblings)
17 siblings, 0 replies; 20+ messages in thread
From: Richard Henderson @ 2016-02-15 3:42 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, aurelien
Using compact branches, when possible, avoids a delay slot nop.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
include/elf.h | 4 +
tcg/mips/tcg-target.c | 270 +++++++++++++++++++++++++++++++++++++++-----------
2 files changed, 218 insertions(+), 56 deletions(-)
diff --git a/include/elf.h b/include/elf.h
index 1098d21..6e52ba0 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -352,6 +352,10 @@ typedef struct {
#define R_MIPS_CALLHI16 30
#define R_MIPS_CALLLO16 31
/*
+ * Incomplete list of MIPS R6 relocation types.
+ */
+#define R_MIPS_PC26_S2 61
+/*
* This range is reserved for vendor specific relocations.
*/
#define R_MIPS_LOVENDOR 100
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index ab72715..447dbcf 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -154,6 +154,19 @@ static inline void reloc_pc16(tcg_insn_unit *pc, tcg_insn_unit *target)
*pc = deposit32(*pc, 0, 16, reloc_pc16_val(pc, target));
}
+static inline uint32_t reloc_pc26_val(tcg_insn_unit *pc, tcg_insn_unit *target)
+{
+ /* Let the compiler perform the right-shift as part of the arithmetic. */
+ ptrdiff_t disp = target - (pc + 1);
+ tcg_debug_assert(disp == sextract32(disp, 0, 26));
+ return disp & 0x1ffffff;
+}
+
+static inline void reloc_pc26(tcg_insn_unit *pc, tcg_insn_unit *target)
+{
+ *pc = deposit32(*pc, 0, 26, reloc_pc16_val(pc, target));
+}
+
static inline uint32_t reloc_26_val(tcg_insn_unit *pc, tcg_insn_unit *target)
{
tcg_debug_assert((((uintptr_t)pc ^ (uintptr_t)target) & 0xf0000000) == 0);
@@ -168,9 +181,17 @@ static inline void reloc_26(tcg_insn_unit *pc, tcg_insn_unit *target)
static void patch_reloc(tcg_insn_unit *code_ptr, int type,
intptr_t value, intptr_t addend)
{
- tcg_debug_assert(type == R_MIPS_PC16);
tcg_debug_assert(addend == 0);
- reloc_pc16(code_ptr, (tcg_insn_unit *)value);
+ switch (type) {
+ case R_MIPS_PC16:
+ reloc_pc16(code_ptr, (tcg_insn_unit *)value);
+ break;
+ case R_MIPS_PC26_S2:
+ reloc_pc26(code_ptr, (tcg_insn_unit *)value);
+ break;
+ default:
+ tcg_abort();
+ }
}
#define TCG_CT_CONST_ZERO 0x100
@@ -288,7 +309,10 @@ typedef enum {
OPC_BEQ = 004 << 26,
OPC_BNE = 005 << 26,
OPC_BLEZ = 006 << 26,
+ OPC_BGEUC = OPC_BLEZ, /* R6: rs != 0, rt != 0, rs != rt */
OPC_BGTZ = 007 << 26,
+ OPC_BLTUC = OPC_BGTZ, /* R6: rs != 0, rt != 0, rs != rt */
+ OPC_BEQC = 010 << 26, /* R6: rs > rt */
OPC_ADDIU = 011 << 26,
OPC_SLTI = 012 << 26,
OPC_SLTIU = 013 << 26,
@@ -297,6 +321,9 @@ typedef enum {
OPC_XORI = 016 << 26,
OPC_LUI = 017 << 26,
OPC_AUI = OPC_LUI,
+ OPC_BGEC = 026 << 26,
+ OPC_BLTC = 027 << 26,
+ OPC_BNEC = 030 << 26, /* R6: rs > rt */
OPC_DADDIU = 031 << 26,
OPC_DAUI = 035 << 26,
OPC_LB = 040 << 26,
@@ -308,6 +335,7 @@ typedef enum {
OPC_SB = 050 << 26,
OPC_SH = 051 << 26,
OPC_SW = 053 << 26,
+ OPC_BC = 062 << 26,
OPC_LD = 067 << 26,
OPC_SD = 077 << 26,
@@ -421,6 +449,33 @@ typedef enum {
? OPC_SRL : OPC_DSRL,
} MIPSInsn;
+static inline void tcg_out_nop(TCGContext *s)
+{
+ tcg_out32(s, 0);
+}
+
+/*
+ * Protect against a mips r6 forbidden slot. If the previously
+ * emitted insn has a forbidden slot, emit a nop.
+ */
+
+static void nop_forbidden_slot(TCGContext *s)
+{
+ if (use_mips32r6_instructions && s->code_ptr > s->code_buf) {
+ tcg_insn_unit prev = s->code_ptr[-1];
+ switch (prev & 0xfc000000u) {
+ case OPC_BGEC:
+ case OPC_BLTC:
+ case OPC_BGEUC:
+ case OPC_BLTUC:
+ case OPC_BEQC:
+ case OPC_BNEC:
+ tcg_out_nop(s);
+ break;
+ }
+ }
+}
+
/*
* Type reg
*/
@@ -496,17 +551,30 @@ static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm,
/*
* Type branch
*/
-static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc,
- TCGReg rt, TCGReg rs)
+static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs)
{
+ uint16_t offset;
+
+ nop_forbidden_slot(s);
+
/* We pay attention here to not modify the branch target by reading
the existing value and using it again. This ensure that caches and
memory are kept coherent during retranslation. */
- uint16_t offset = (uint16_t)*s->code_ptr;
-
+ offset = (uint16_t)*s->code_ptr;
tcg_out_opc_imm(s, opc, rt, rs, offset);
}
+static void tcg_out_opc_br_pc16(TCGContext *s, MIPSInsn opc,
+ TCGReg rt, TCGReg rs, TCGLabel *l)
+{
+ tcg_out_opc_br(s, opc, rt, rs);
+ if (l->has_value) {
+ reloc_pc16(s->code_ptr - 1, l->u.value_ptr);
+ } else {
+ tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0);
+ }
+}
+
/*
* Type sa
*/
@@ -552,17 +620,16 @@ static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, void *target)
}
tcg_debug_assert((dest & 3) == 0);
+ /* Since the entire code gen buffer is within the 256MB region,
+ potentially adding a nop doesn't affect the test above. */
+ nop_forbidden_slot(s);
+
inst = opc;
inst |= (dest >> 2) & 0x3ffffff;
tcg_out32(s, inst);
return true;
}
-static inline void tcg_out_nop(TCGContext *s)
-{
- tcg_out32(s, 0);
-}
-
static inline void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
{
tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa);
@@ -1018,59 +1085,136 @@ static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
[TCG_COND_GE] = OPC_BGEZ,
};
- MIPSInsn s_opc = OPC_SLTU;
- MIPSInsn b_opc;
+ MIPSInsn b_opc = 0;
+ bool compact = false;
+ TCGReg rs = arg1, rt = arg2;
int cmp_map;
- switch (cond) {
- case TCG_COND_EQ:
- b_opc = OPC_BEQ;
- break;
- case TCG_COND_NE:
- b_opc = OPC_BNE;
- break;
+ /* We shouldn't expect to have arg1 == arg2, as the TCG optimizer
+ should have eliminated all such. However, the R6 encodings do
+ not allow this situation, so e.g. if the optimizer is disabled
+ we must fall back to normal compares. */
+ if (use_mips32r6_instructions && arg1 != arg2) {
+ switch (cond) {
+ case TCG_COND_EQ:
+ case TCG_COND_NE:
+ if (rs < rt) {
+ rs = arg2, rt = arg1;
+ }
+ b_opc = cond == TCG_COND_EQ ? OPC_BEQC : OPC_BNEC;
+ compact = true;
+ break;
- case TCG_COND_LT:
- case TCG_COND_GT:
- case TCG_COND_LE:
- case TCG_COND_GE:
- if (arg2 == 0) {
- b_opc = b_zero[cond];
- arg2 = arg1;
- arg1 = 0;
+ case TCG_COND_LE:
+ case TCG_COND_GT:
+ /* Swap arguments to turn LE to GE or GT to LT.
+ This also produces BLEZC/BGTZC when arg2 = 0. */
+ rs = arg2, rt = arg1;
+ if (rt == TCG_REG_ZERO) {
+ break;
+ }
+ b_opc = cond == TCG_COND_LE ? OPC_BGEC : OPC_BLTC;
+ compact = true;
break;
- }
- s_opc = OPC_SLT;
- /* FALLTHRU */
- case TCG_COND_LTU:
- case TCG_COND_GTU:
- case TCG_COND_LEU:
- case TCG_COND_GEU:
- cmp_map = mips_cmp_map[cond];
- if (cmp_map & MIPS_CMP_SWAP) {
- TCGReg t = arg1;
- arg1 = arg2;
- arg2 = t;
+ case TCG_COND_GE:
+ case TCG_COND_LT:
+ if (rs == TCG_REG_ZERO) {
+ break;
+ }
+ /* The encoding of BGEZC/BLTZC requires rs = rt. */
+ if (rt == TCG_REG_ZERO) {
+ rt = rs;
+ }
+ b_opc = cond == TCG_COND_GE ? OPC_BGEC : OPC_BLTC;
+ compact = true;
+ break;
+
+ case TCG_COND_LEU:
+ /* Swap arguments to turn LE to GE. */
+ rs = arg2, rt = arg1;
+ /* FALLTHRU */
+ case TCG_COND_GEU:
+ if (rs == TCG_REG_ZERO || rt == TCG_REG_ZERO) {
+ break;
+ }
+ b_opc = OPC_BGEUC;
+ compact = true;
+ break;
+
+ case TCG_COND_GTU:
+ /* Swap arguments to turn GT to LT. */
+ rs = arg2, rt = arg1;
+ /* FALLTHRU */
+ case TCG_COND_LTU:
+ if (rs == TCG_REG_ZERO || rt == TCG_REG_ZERO) {
+ break;
+ }
+ b_opc = OPC_BLTUC;
+ compact = true;
+ break;
+
+ default:
+ tcg_abort();
+ break;
}
- tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2);
- b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE);
- arg1 = TCG_TMP0;
- arg2 = TCG_REG_ZERO;
- break;
+ }
- default:
- tcg_abort();
- break;
+ if (b_opc == 0) {
+ MIPSInsn s_opc = OPC_SLTU;
+
+ switch (cond) {
+ case TCG_COND_EQ:
+ b_opc = OPC_BEQ;
+ break;
+ case TCG_COND_NE:
+ b_opc = OPC_BNE;
+ break;
+
+ case TCG_COND_LT:
+ case TCG_COND_GT:
+ case TCG_COND_LE:
+ case TCG_COND_GE:
+ if (arg2 == 0) {
+ b_opc = b_zero[cond];
+ rs = arg1;
+ rt = 0;
+ break;
+ }
+ s_opc = OPC_SLT;
+ /* FALLTHRU */
+
+ case TCG_COND_LTU:
+ case TCG_COND_GTU:
+ case TCG_COND_LEU:
+ case TCG_COND_GEU:
+ cmp_map = mips_cmp_map[cond];
+ if (cmp_map & MIPS_CMP_SWAP) {
+ TCGReg t = arg1;
+ arg1 = arg2;
+ arg2 = t;
+ }
+ tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2);
+ if (use_mips32r6_instructions) {
+ b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQC : OPC_BNEC);
+ compact = true;
+ } else {
+ b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE);
+ }
+ rs = TCG_TMP0;
+ rt = TCG_REG_ZERO;
+ break;
+
+ default:
+ tcg_abort();
+ break;
+ }
}
- tcg_out_opc_br(s, b_opc, arg1, arg2);
- if (l->has_value) {
- reloc_pc16(s->code_ptr - 1, l->u.value_ptr);
- } else {
- tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0);
+ tcg_out_opc_br_pc16(s, b_opc, rt, rs, l);
+ if (!compact) {
+ tcg_out_nop(s);
}
- tcg_out_nop(s);
}
static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1,
@@ -1807,6 +1951,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_goto_tb:
if (s->tb_jmp_offset) {
/* direct jump method */
+ nop_forbidden_slot(s);
s->tb_jmp_offset[a0] = tcg_current_code_size(s);
/* Avoid clobbering the address during retranslation. */
tcg_out32(s, OPC_J | (*(uint32_t *)s->code_ptr & 0x3ffffff));
@@ -1820,8 +1965,21 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
s->tb_next_offset[a0] = tcg_current_code_size(s);
break;
case INDEX_op_br:
- tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO,
- arg_label(a0));
+ {
+ TCGLabel *l = arg_label(a0);
+ if (use_mips32r6_instructions) {
+ nop_forbidden_slot(s);
+ tcg_out32(s, OPC_BC);
+ if (l->has_value) {
+ reloc_pc26(s->code_ptr - 1, l->u.value_ptr);
+ } else {
+ tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC26_S2, l, 0);
+ }
+ } else {
+ tcg_out_opc_br_pc16(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO, l);
+ tcg_out_nop(s);
+ }
+ }
break;
case INDEX_op_ld8u_i32:
--
2.5.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH v2 16/16] tcg-mips: Use mipsr6 instructions in calls
2016-02-15 3:42 [Qemu-devel] [PATCH v2 00/16] tcg mips64 and mips r6 improvements Richard Henderson
` (14 preceding siblings ...)
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 15/16] tcg-mips: Use mipsr6 instructions in branches Richard Henderson
@ 2016-02-15 3:42 ` Richard Henderson
2016-02-15 3:47 ` [Qemu-devel] [PATCH v2 00/16] tcg mips64 and mips r6 improvements Richard Henderson
2016-02-28 23:51 ` Aurelien Jarno
17 siblings, 0 replies; 20+ messages in thread
From: Richard Henderson @ 2016-02-15 3:42 UTC (permalink / raw)
To: qemu-devel; +Cc: mark.cave-ayland, aurelien
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/mips/tcg-target.c | 32 ++++++++++++++++++++------------
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 447dbcf..16118f7 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -336,7 +336,9 @@ typedef enum {
OPC_SH = 051 << 26,
OPC_SW = 053 << 26,
OPC_BC = 062 << 26,
+ OPC_JIC = 066 << 26,
OPC_LD = 067 << 26,
+ OPC_JIALC = 076 << 26,
OPC_SD = 077 << 26,
OPC_SPECIAL = 000 << 26,
@@ -1364,28 +1366,32 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
}
}
-static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail)
+static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg,
+ bool tail, bool want_delay)
{
/* Note that the ABI requires the called function's address to be
loaded into T9, even if a direct branch is in range. */
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg);
/* But do try a direct branch, allowing the cpu better insn prefetch. */
- if (tail) {
- if (!tcg_out_opc_jmp(s, OPC_J, arg)) {
- tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0);
- }
+ if (tcg_out_opc_jmp(s, tail ? OPC_J : OPC_JAL, arg)) {
+ /* jmp emitted */
+ } else if (use_mips32r6_instructions && !want_delay) {
+ tcg_out_opc_reg(s, tail ? OPC_JIC : OPC_JIALC, 0, TCG_REG_T9, 0);
+ return;
+ } else if (tail) {
+ tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0);
} else {
- if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) {
- tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0);
- }
+ tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0);
+ }
+ if (!want_delay) {
+ tcg_out_nop(s);
}
}
static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg)
{
- tcg_out_call_int(s, arg, false);
- tcg_out_nop(s);
+ tcg_out_call_int(s, arg, false, false);
}
#if defined(CONFIG_SOFTMMU)
@@ -1596,7 +1602,8 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
}
i = tcg_out_call_iarg_imm(s, i, oi);
i = tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr);
- tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], false);
+ tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)],
+ false, true);
/* delay slot */
tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
@@ -1660,7 +1667,8 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
computation to take place in the return address register. */
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr);
i = tcg_out_call_iarg_reg(s, i, TCG_REG_RA);
- tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true);
+ tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)],
+ true, true);
/* delay slot */
tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
}
--
2.5.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [Qemu-devel] [PATCH v2 00/16] tcg mips64 and mips r6 improvements
2016-02-15 3:42 [Qemu-devel] [PATCH v2 00/16] tcg mips64 and mips r6 improvements Richard Henderson
` (15 preceding siblings ...)
2016-02-15 3:42 ` [Qemu-devel] [PATCH v2 16/16] tcg-mips: Use mipsr6 instructions in calls Richard Henderson
@ 2016-02-15 3:47 ` Richard Henderson
2016-02-28 23:51 ` Aurelien Jarno
17 siblings, 0 replies; 20+ messages in thread
From: Richard Henderson @ 2016-02-15 3:47 UTC (permalink / raw)
To: qemu-devel; +Cc: James Hogan, mark.cave-ayland, aurelien
On 02/15/2016 02:42 PM, Richard Henderson wrote:
> Changes since v1:
> * Some bugs pointed out by Mark fixed.
Bah. Brain fart -- not Mark, James.
Which also means I used the wrong --cc option too.
Ho hum.
r~
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [Qemu-devel] [PATCH v2 00/16] tcg mips64 and mips r6 improvements
2016-02-15 3:42 [Qemu-devel] [PATCH v2 00/16] tcg mips64 and mips r6 improvements Richard Henderson
` (16 preceding siblings ...)
2016-02-15 3:47 ` [Qemu-devel] [PATCH v2 00/16] tcg mips64 and mips r6 improvements Richard Henderson
@ 2016-02-28 23:51 ` Aurelien Jarno
17 siblings, 0 replies; 20+ messages in thread
From: Aurelien Jarno @ 2016-02-28 23:51 UTC (permalink / raw)
To: Richard Henderson; +Cc: mark.cave-ayland, qemu-devel
On 2016-02-15 14:42, Richard Henderson wrote:
> Changes since v1:
> * Some bugs pointed out by Mark fixed.
> * Canonicalize the whole file on tcg_debug_assert.
> * Switch bswap code to subroutine earlier; the first patch is
> standalone for mips32, and there is no longer an intermediate
> patch with inline bswap for mips64.
> * Use NAL for pre-r6 mips64 loading of the slow path return address.
>
Thanks a lot for working on that, it's something I have on my TODO list
for months. I have finally found time to have a look and give a try over
the week-end (sorry about the delay).
It seems to work perfectly for 64-bit guests on mips64el but 32-bit
guests end-up quickly in a segmentation fault. It's easily reproducible
by starting qemu-system-i386 on a mips64el host, it crashes when
executing seabios.
More problematic it seems that the patch "Adjust qemu_ld/st for mips64"
causes a regression on at least a big-endian 32-bit host running
qemu-system-i386. It is reproducible by booting a Debian i386 wheezy
guest on such a system. Unfortunately the week-end was too short for
finding the issue, I'll continue looking in the next days.
I have a few comments on the individual patches, I'll send them asap.
Note that I don't have an R6 machine, so I haven't been able to test
that part.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 20+ messages in thread