From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60224) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aWPfp-0005EI-S4 for qemu-devel@nongnu.org; Thu, 18 Feb 2016 09:35:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aWPfo-0007tN-QT for qemu-devel@nongnu.org; Thu, 18 Feb 2016 09:35:17 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:38427) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aWPfo-0007rP-K7 for qemu-devel@nongnu.org; Thu, 18 Feb 2016 09:35:16 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.84) (envelope-from ) id 1aWPfh-0001pf-CL for qemu-devel@nongnu.org; Thu, 18 Feb 2016 14:35:09 +0000 From: Peter Maydell Date: Thu, 18 Feb 2016 14:34:45 +0000 Message-Id: <1455806108-6961-14-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1455806108-6961-1-git-send-email-peter.maydell@linaro.org> References: <1455806108-6961-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 13/36] target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: Alistair Francis Signed-off-by: Aaron Lindsay Signed-off-by: Alistair Francis Tested-by: Nathan Rossi Reviewed-by: Peter Maydell Message-id: 50deeafb24958a5b6d7f594b5dda399a022c0e5b.1455060548.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell --- target-arm/helper.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 6a4ec01..9e47f3d 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1057,6 +1057,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .accessfn = pmreg_access, .writefn = pmovsr_write, .raw_writefn = raw_write }, + { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3, + .access = PL0_RW, .accessfn = pmreg_access, + .type = ARM_CP_ALIAS, + .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr), + .writefn = pmovsr_write, + .raw_writefn = raw_write }, /* Unimplemented so WI. */ { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4, .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP }, @@ -1107,6 +1114,11 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .access = PL1_RW, .type = ARM_CP_ALIAS, .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), .writefn = pmintenclr_write, }, + { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, + .access = PL1_RW, .type = ARM_CP_ALIAS, + .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), + .writefn = pmintenclr_write }, { .name = "VBAR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .writefn = vbar_write, -- 1.9.1