From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60596) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aWPg1-0005Wq-G6 for qemu-devel@nongnu.org; Thu, 18 Feb 2016 09:35:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aWPg0-00083A-8Q for qemu-devel@nongnu.org; Thu, 18 Feb 2016 09:35:29 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:38427) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aWPg0-0007rP-1A for qemu-devel@nongnu.org; Thu, 18 Feb 2016 09:35:28 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.84) (envelope-from ) id 1aWPfh-0001pj-EG for qemu-devel@nongnu.org; Thu, 18 Feb 2016 14:35:09 +0000 From: Peter Maydell Date: Thu, 18 Feb 2016 14:34:46 +0000 Message-Id: <1455806108-6961-15-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1455806108-6961-1-git-send-email-peter.maydell@linaro.org> References: <1455806108-6961-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 14/36] target-arm: Add PMUSERENR_EL0 register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: Alistair Francis The Linux kernel accesses this register early in its setup. Signed-off-by: Christopher Covington Signed-off-by: Alistair Francis Reviewed-by: Peter Maydell Message-id: b30d536cb16ec57b4412172bb6dbc3f00d293e7d.1455060548.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell --- target-arm/helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 9e47f3d..5a0447b 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1105,6 +1105,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), .resetvalue = 0, .writefn = pmuserenr_write, .raw_writefn = raw_write }, + { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0, + .access = PL0_R | PL1_RW, .type = ARM_CP_ALIAS, + .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr), + .resetvalue = 0, + .writefn = pmuserenr_write, .raw_writefn = raw_write }, { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), -- 1.9.1