* [Qemu-devel] [PULL 00/36] target-arm queue
@ 2016-02-18 15:20 Peter Maydell
2016-02-18 15:50 ` Peter Maydell
0 siblings, 1 reply; 13+ messages in thread
From: Peter Maydell @ 2016-02-18 15:20 UTC (permalink / raw)
To: qemu-devel
Second try, with the typedef issue fixed.
-- PMM
The following changes since commit 339b665c883b209982fa161dc090ffaf242ab12b:
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.6-20160218' into staging (2016-02-18 10:29:47 +0000)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160218-1
for you to fetch changes up to 5d83e348e7f6499f27b6431b0d91af8dcfb06763:
hw/timer: QOM'ify pxa2xx_timer (2016-02-18 14:50:51 +0000)
----------------------------------------------------------------
target-arm queue:
* implement or fix various EL3 trap behaviour for system registers
* clean up the trap/undef handling of the SRS instruction
* add some missing AArch64 performance monitor system registers
* implement reset for the PL061 GPIO device
* QOMify sd.c and the pxa2xx_mmci device
* SD card emulation fixes for booting Tianocore UEFI on RPi2
* QOMify various ARM timer devices
----------------------------------------------------------------
Alistair Francis (3):
target-arm: Add the pmceid0 and pmceid1 registers
target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers
target-arm: Add PMUSERENR_EL0 register
Andrew Baumann (3):
hw/sd: implement CMD23 (SET_BLOCK_COUNT) for MMC compatibility
hw/sd: model a power-up delay, as a workaround for an EDK2 bug
hw/sd: use guest error logging rather than fprintf to stderr
Peter Maydell (21):
target-arm: correct CNTFRQ access rights
target-arm: Fix handling of SCR.SMD
target-arm: Implement MDCR_EL3.TDOSA and MDCR_EL2.TDOSA traps
target-arm: Implement MDCR_EL2.TDRA traps
target-arm: Implement MDCR_EL3.TDA and MDCR_EL2.TDA traps
target-arm: Report correct syndrome for FPEXC32_EL2 traps
target-arm: Clean up trap/undef handling of SRS
target-arm: Move get/set_r13_banked() to op_helper.c
target-arm: Move bank_number() into internals.h
target-arm: Combine user-only and softmmu get/set_r13_banked()
target-arm: UNDEF in the UNPREDICTABLE SRS-from-System case
hw/sd/sdhci.c: Remove x-drive property
hw/sd/sd.c: QOMify
hw/sd/sd.c: Convert sd_reset() function into Device reset method
hw/sd: Add QOM bus which SD cards plug in to
hw/sd/sdhci.c: Update to use SDBus APIs
sdhci_sysbus: Create SD card device in users, not the device itself
hw/sd/pxa2xx_mmci: convert to SysBusDevice object
hw/sd/pxa2xx_mmci: Update to use new SDBus APIs
hw/sd/pxa2xx_mmci: Convert to VMStateDescription
hw/sd/pxa2xx_mmci: Add reset function
Wei Huang (2):
ARM: PL061: Clear PL061 device state after reset
ARM: PL061: Cleaning field of PL061 device state
xiaoqiang.zhao (7):
hw/timer: QOM'ify arm_timer (pass 1)
hw/timer: QOM'ify arm_timer (pass 2)
hw/timer: QOM'ify exynos4210_mct
hw/timer: QOM'ify exynos4210_pwm
hw/timer: QOM'ify exynos4210_rtc
hw/timer: QOM'ify pl031
hw/timer: QOM'ify pxa2xx_timer
hw/arm/xilinx_zynq.c | 17 ++-
hw/arm/xlnx-ep108.c | 21 ++++
hw/arm/xlnx-zynqmp.c | 8 ++
hw/gpio/pl061.c | 37 ++++--
hw/sd/Makefile.objs | 2 +-
hw/sd/core.c | 146 ++++++++++++++++++++++
hw/sd/pxa2xx_mmci.c | 304 ++++++++++++++++++++++++++++++----------------
hw/sd/sd.c | 289 ++++++++++++++++++++++++++++++++++++-------
hw/sd/sdhci.c | 82 +++++++------
hw/timer/arm_timer.c | 42 +++----
hw/timer/exynos4210_mct.c | 12 +-
hw/timer/exynos4210_pwm.c | 12 +-
hw/timer/exynos4210_rtc.c | 12 +-
hw/timer/pl031.c | 11 +-
hw/timer/pxa2xx_timer.c | 36 +++---
include/hw/sd/sd.h | 65 ++++++++++
include/hw/sd/sdhci.h | 3 +-
target-arm/cpu-qom.h | 2 +
target-arm/cpu.c | 2 +
target-arm/cpu.h | 29 +++++
target-arm/cpu64.c | 2 +
target-arm/helper.c | 214 ++++++++++++++++++++------------
target-arm/internals.h | 26 +++-
target-arm/op_helper.c | 51 +++++++-
target-arm/translate.c | 67 +++++++++-
25 files changed, 1144 insertions(+), 348 deletions(-)
create mode 100644 hw/sd/core.c
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [PULL 00/36] target-arm queue
2016-02-18 15:20 [Qemu-devel] [PULL 00/36] target-arm queue Peter Maydell
@ 2016-02-18 15:50 ` Peter Maydell
0 siblings, 0 replies; 13+ messages in thread
From: Peter Maydell @ 2016-02-18 15:50 UTC (permalink / raw)
To: QEMU Developers
On 18 February 2016 at 15:20, Peter Maydell <peter.maydell@linaro.org> wrote:
> Second try, with the typedef issue fixed.
>
> -- PMM
>
>
> The following changes since commit 339b665c883b209982fa161dc090ffaf242ab12b:
>
> Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.6-20160218' into staging (2016-02-18 10:29:47 +0000)
>
> are available in the git repository at:
>
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160218-1
>
> for you to fetch changes up to 5d83e348e7f6499f27b6431b0d91af8dcfb06763:
>
> hw/timer: QOM'ify pxa2xx_timer (2016-02-18 14:50:51 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * implement or fix various EL3 trap behaviour for system registers
> * clean up the trap/undef handling of the SRS instruction
> * add some missing AArch64 performance monitor system registers
> * implement reset for the PL061 GPIO device
> * QOMify sd.c and the pxa2xx_mmci device
> * SD card emulation fixes for booting Tianocore UEFI on RPi2
> * QOMify various ARM timer devices
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Qemu-devel] [PULL 00/36] target-arm queue
@ 2017-09-04 14:39 Peter Maydell
2017-09-04 16:20 ` Peter Maydell
0 siblings, 1 reply; 13+ messages in thread
From: Peter Maydell @ 2017-09-04 14:39 UTC (permalink / raw)
To: qemu-devel
Try #2, with the compile failure in kvm32.c fixed
(trivial change, not resending patches)
thanks
-- PMM
The following changes since commit 98bfaac788be0ca63d7d010c8d4ba100ff1d8278:
Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2017-09-01-v3' into staging (2017-09-04 13:28:09 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170904-1
for you to fetch changes up to 0b8095ec9e924dc00636ab2069d88dec6592a75d:
arm_gicv3_kvm: Fix compile warning (2017-09-04 15:21:56 +0100)
----------------------------------------------------------------
target-arm:
* collection of M profile cleanups and minor bugfixes
* loader: handle ELF files with overlapping zero-init data
* virt: allow PMU instantiation with userspace irqchip
* wdt_aspeed: Add support for the reset width register
* cpu: Define new cpu_transaction_failed() hook
* arm: Support generating CPU exceptions on memory
transaction failures (bus faults)
* Mark some SoC devices as not user-creatable
* arm: Fix aa64 ldp register writeback
* arm_gicv3_kvm: Fix compile warning
----------------------------------------------------------------
Andrew Jeffery (2):
watchdog: wdt_aspeed: Add support for the reset width register
aspeed_soc: Propagate silicon-rev to watchdog
Andrew Jones (4):
hw/arm/virt: add pmu interrupt state
target/arm/kvm: pmu: split init and set-irq stages
hw/arm/virt: allow pmu instantiation with userspace irqchip
target/arm/kvm: pmu: improve error handling
Peter Maydell (25):
target/arm: Use MMUAccessType enum rather than int
target/arm: Don't trap WFI/WFE for M profile
target/arm: Consolidate PMSA handling in get_phys_addr()
target/arm: Tighten up Thumb decode where new v8M insns will be
hw/intc/armv7m_nvic.c: Remove out of date comment
target/arm: Remove incorrect comment about MPU_CTRL
target/arm: Fix outdated comment about exception exit
target/arm: Define and use XPSR bit masks
target/arm: Don't store M profile PRIMASK and FAULTMASK in daif
target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR
target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR
target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed
target/arm: Create and use new function arm_v7m_is_handler_mode()
armv7m_nvic.h: Move from include/hw/arm to include/hw/intc
nvic: Implement "user accesses BusFault" SCS region behaviour
loader: Handle ELF files with overlapping zero-initialized data
loader: Ignore zero-sized ELF segments
memory.h: Move MemTxResult type to memattrs.h
cpu: Define new cpu_transaction_failed() hook
cputlb: Support generating CPU exceptions on memory transaction failures
boards.h: Define new flag ignore_memory_transaction_failures
hw/arm: Set ignore_memory_transaction_failures for most ARM boards
target/arm: Factor out fault delivery code
target/arm: Allow deliver_fault() caller to specify EA bit
target/arm: Implement new do_transaction_failed hook
Philippe Mathieu-Daudé (1):
hw/arm: use defined type name instead of hard-coded string
Pranith Kumar (1):
arm_gicv3_kvm: Fix compile warning
Richard Henderson (1):
target/arm: Fix aa64 ldp register writeback
Thomas Huth (2):
hw/arm/aspeed_soc: Mark devices as user_creatable = false
hw/arm/digic: Mark device with user_creatable = false
include/exec/memattrs.h | 10 +++
include/exec/memory.h | 10 ---
include/hw/arm/armv7m.h | 2 +-
include/hw/boards.h | 11 +++
include/hw/elf_ops.h | 72 +++++++++++++--
include/hw/{arm => intc}/armv7m_nvic.h | 0
include/hw/watchdog/wdt_aspeed.h | 2 +
include/qom/cpu.h | 27 ++++++
softmmu_template.h | 4 +-
target/arm/cpu.h | 56 +++++++++---
target/arm/internals.h | 15 +++-
target/arm/kvm_arm.h | 9 +-
accel/tcg/cputlb.c | 32 ++++++-
hw/arm/armv7m.c | 4 +-
hw/arm/aspeed.c | 3 +
hw/arm/aspeed_soc.c | 4 +
hw/arm/collie.c | 1 +
hw/arm/cubieboard.c | 1 +
hw/arm/digic.c | 2 +
hw/arm/digic_boards.c | 1 +
hw/arm/exynos4210.c | 4 +-
hw/arm/exynos4_boards.c | 2 +
hw/arm/gumstix.c | 2 +
hw/arm/highbank.c | 13 ++-
hw/arm/imx25_pdk.c | 1 +
hw/arm/integratorcp.c | 1 +
hw/arm/kzm.c | 1 +
hw/arm/mainstone.c | 1 +
hw/arm/musicpal.c | 1 +
hw/arm/netduino2.c | 1 +
hw/arm/nseries.c | 2 +
hw/arm/omap_sx1.c | 2 +
hw/arm/palm.c | 1 +
hw/arm/raspi.c | 1 +
hw/arm/realview.c | 10 ++-
hw/arm/sabrelite.c | 1 +
hw/arm/spitz.c | 4 +
hw/arm/stellaris.c | 2 +
hw/arm/tosa.c | 1 +
hw/arm/versatilepb.c | 2 +
hw/arm/vexpress.c | 7 +-
hw/arm/virt.c | 12 ++-
hw/arm/xilinx_zynq.c | 15 ++--
hw/arm/xlnx-ep108.c | 2 +
hw/arm/z2.c | 1 +
hw/intc/arm_gicv3_kvm.c | 2 +-
hw/intc/armv7m_nvic.c | 68 +++++++++-----
hw/watchdog/wdt_aspeed.c | 93 ++++++++++++++++---
qom/cpu.c | 7 ++
target/arm/cpu.c | 8 +-
target/arm/helper.c | 124 ++++++++++++-------------
target/arm/kvm.c | 6 +-
target/arm/kvm32.c | 8 +-
target/arm/kvm64.c | 63 +++++++------
target/arm/machine.c | 54 ++++++++++-
target/arm/op_helper.c | 160 ++++++++++++++++++++++-----------
target/arm/translate-a64.c | 29 +++---
target/arm/translate.c | 106 ++++++++++++++++------
58 files changed, 795 insertions(+), 289 deletions(-)
rename include/hw/{arm => intc}/armv7m_nvic.h (100%)
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [PULL 00/36] target-arm queue
2017-09-04 14:39 Peter Maydell
@ 2017-09-04 16:20 ` Peter Maydell
0 siblings, 0 replies; 13+ messages in thread
From: Peter Maydell @ 2017-09-04 16:20 UTC (permalink / raw)
To: QEMU Developers
On 4 September 2017 at 15:39, Peter Maydell <peter.maydell@linaro.org> wrote:
> Try #2, with the compile failure in kvm32.c fixed
> (trivial change, not resending patches)
Rats, this doesn't work either -- turns out that
boards.h: Define new flag ignore_memory_transaction_failures
breaks the usermode emulators.
I'm going to drop:
> boards.h: Define new flag ignore_memory_transaction_failures
> hw/arm: Set ignore_memory_transaction_failures for most ARM boards
> target/arm: Implement new do_transaction_failed hook
and resend the pullreq.
thanks
-- PMM
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Qemu-devel] [PULL 00/36] target-arm queue
@ 2017-09-04 12:25 Peter Maydell
0 siblings, 0 replies; 13+ messages in thread
From: Peter Maydell @ 2017-09-04 12:25 UTC (permalink / raw)
To: qemu-devel
First arm pullreq of the 2.11 cycle. I know I still have some
more stuff on my queue to review, but 36 patches is big enough
as it is; I expect I'll do another pull later this week.
thanks
-- PMM
The following changes since commit 32f0f68bb77289b75a82925f712bb52e16eac3ba:
Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-request' into staging (2017-09-01 17:28:54 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170904
for you to fetch changes up to 1e35c4ce33a94cf78dbf639695cb877ef35920b0:
arm_gicv3_kvm: Fix compile warning (2017-09-04 12:09:32 +0100)
----------------------------------------------------------------
target-arm:
* collection of M profile cleanups and minor bugfixes
* loader: handle ELF files with overlapping zero-init data
* virt: allow PMU instantiation with userspace irqchip
* wdt_aspeed: Add support for the reset width register
* cpu: Define new cpu_transaction_failed() hook
* arm: Support generating CPU exceptions on memory
transaction failures (bus faults)
* Mark some SoC devices as not user-creatable
* arm: Fix aa64 ldp register writeback
* arm_gicv3_kvm: Fix compile warning
----------------------------------------------------------------
Andrew Jeffery (2):
watchdog: wdt_aspeed: Add support for the reset width register
aspeed_soc: Propagate silicon-rev to watchdog
Andrew Jones (4):
hw/arm/virt: add pmu interrupt state
target/arm/kvm: pmu: split init and set-irq stages
hw/arm/virt: allow pmu instantiation with userspace irqchip
target/arm/kvm: pmu: improve error handling
Peter Maydell (25):
target/arm: Use MMUAccessType enum rather than int
target/arm: Don't trap WFI/WFE for M profile
target/arm: Consolidate PMSA handling in get_phys_addr()
target/arm: Tighten up Thumb decode where new v8M insns will be
hw/intc/armv7m_nvic.c: Remove out of date comment
target/arm: Remove incorrect comment about MPU_CTRL
target/arm: Fix outdated comment about exception exit
target/arm: Define and use XPSR bit masks
target/arm: Don't store M profile PRIMASK and FAULTMASK in daif
target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR
target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR
target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed
target/arm: Create and use new function arm_v7m_is_handler_mode()
armv7m_nvic.h: Move from include/hw/arm to include/hw/intc
nvic: Implement "user accesses BusFault" SCS region behaviour
loader: Handle ELF files with overlapping zero-initialized data
loader: Ignore zero-sized ELF segments
memory.h: Move MemTxResult type to memattrs.h
cpu: Define new cpu_transaction_failed() hook
cputlb: Support generating CPU exceptions on memory transaction failures
boards.h: Define new flag ignore_memory_transaction_failures
hw/arm: Set ignore_memory_transaction_failures for most ARM boards
target/arm: Factor out fault delivery code
target/arm: Allow deliver_fault() caller to specify EA bit
target/arm: Implement new do_transaction_failed hook
Philippe Mathieu-Daudé (1):
hw/arm: use defined type name instead of hard-coded string
Pranith Kumar (1):
arm_gicv3_kvm: Fix compile warning
Richard Henderson (1):
target/arm: Fix aa64 ldp register writeback
Thomas Huth (2):
hw/arm/aspeed_soc: Mark devices as user_creatable = false
hw/arm/digic: Mark device with user_creatable = false
include/exec/memattrs.h | 10 +++
include/exec/memory.h | 10 ---
include/hw/arm/armv7m.h | 2 +-
include/hw/boards.h | 11 +++
include/hw/elf_ops.h | 72 +++++++++++++--
include/hw/{arm => intc}/armv7m_nvic.h | 0
include/hw/watchdog/wdt_aspeed.h | 2 +
include/qom/cpu.h | 27 ++++++
softmmu_template.h | 4 +-
target/arm/cpu.h | 56 +++++++++---
target/arm/internals.h | 15 +++-
target/arm/kvm_arm.h | 9 +-
accel/tcg/cputlb.c | 32 ++++++-
hw/arm/armv7m.c | 4 +-
hw/arm/aspeed.c | 3 +
hw/arm/aspeed_soc.c | 4 +
hw/arm/collie.c | 1 +
hw/arm/cubieboard.c | 1 +
hw/arm/digic.c | 2 +
hw/arm/digic_boards.c | 1 +
hw/arm/exynos4210.c | 4 +-
hw/arm/exynos4_boards.c | 2 +
hw/arm/gumstix.c | 2 +
hw/arm/highbank.c | 13 ++-
hw/arm/imx25_pdk.c | 1 +
hw/arm/integratorcp.c | 1 +
hw/arm/kzm.c | 1 +
hw/arm/mainstone.c | 1 +
hw/arm/musicpal.c | 1 +
hw/arm/netduino2.c | 1 +
hw/arm/nseries.c | 2 +
hw/arm/omap_sx1.c | 2 +
hw/arm/palm.c | 1 +
hw/arm/raspi.c | 1 +
hw/arm/realview.c | 10 ++-
hw/arm/sabrelite.c | 1 +
hw/arm/spitz.c | 4 +
hw/arm/stellaris.c | 2 +
hw/arm/tosa.c | 1 +
hw/arm/versatilepb.c | 2 +
hw/arm/vexpress.c | 7 +-
hw/arm/virt.c | 12 ++-
hw/arm/xilinx_zynq.c | 15 ++--
hw/arm/xlnx-ep108.c | 2 +
hw/arm/z2.c | 1 +
hw/intc/arm_gicv3_kvm.c | 2 +-
hw/intc/armv7m_nvic.c | 68 +++++++++-----
hw/watchdog/wdt_aspeed.c | 93 ++++++++++++++++---
qom/cpu.c | 7 ++
target/arm/cpu.c | 8 +-
target/arm/helper.c | 124 ++++++++++++-------------
target/arm/kvm.c | 6 +-
target/arm/kvm32.c | 7 +-
target/arm/kvm64.c | 63 +++++++------
target/arm/machine.c | 54 ++++++++++-
target/arm/op_helper.c | 160 ++++++++++++++++++++++-----------
target/arm/translate-a64.c | 29 +++---
target/arm/translate.c | 106 ++++++++++++++++------
58 files changed, 795 insertions(+), 288 deletions(-)
rename include/hw/{arm => intc}/armv7m_nvic.h (100%)
^ permalink raw reply [flat|nested] 13+ messages in thread* [Qemu-devel] [PULL 00/36] target-arm queue
@ 2017-01-19 14:09 Peter Maydell
0 siblings, 0 replies; 13+ messages in thread
From: Peter Maydell @ 2017-01-19 14:09 UTC (permalink / raw)
To: qemu-devel
ARM queue -- the big bit here is the virtualization
stuff for the GIC and correspondingly enabling it in
the virt board.
thanks
-- PMM
The following changes since commit ab4b92760498e097ff668f0e9c83aa87a2ec1128:
Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' into staging (2017-01-17 16:54:09 +0000)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170119
for you to fetch changes up to 245c8cbc4e4f0f8b6c3dfaab2090d1d55f94d360:
hw/arm/virt: Add board property to enable EL2 (2017-01-19 13:40:23 +0000)
----------------------------------------------------------------
target-arm queue:
* support virtualization in GICv3
* enable EL2 in AArch64 CPU models
* allow EL2 to be enabled on 'virt' board via -machine virtualization=on
* aspeed: SMC improvements
* m25p80: support die erase command
* m25p80: Add Quad Page Program 4byte
* m25p80: Improve 1GiB Micron flash definition
* arm: Uniquely name imx25 I2C buses
----------------------------------------------------------------
Alastair D'Silva (1):
arm: Uniquely name imx25 I2C buses.
Andrew Jones (1):
hw/arm/virt-acpi-build: use SMC if booting in EL2
Ard Biesheuvel (1):
hw/arm/virt-acpi - reserve ECAM space as PNP0C02 device
Cédric Le Goater (10):
aspeed/smc: remove call to reset in realize function
aspeed/smc: remove call to aspeed_smc_update_cs() in reset function
aspeed/smc: rework the prototype of the AspeedSMCFlash helper routines
aspeed/smc: autostrap CE0/1 configuration
aspeed/smc: unfold the AspeedSMCController array
aspeed/smc: adjust the size of the register region
aspeed/smc: handle SPI flash Command mode
aspeed/smc: reset flash after each test
aspeed/smc: extend tests for Command mode
aspeed: use first FMC flash as a boot ROM
Marcin Krzeminski (3):
block: m25p80: Add Quad Page Program 4byte
block: m25p80: Introduce die erase command
block: m25p80: Improve 1GiB Micron flash definition
Peter Maydell (19):
target/arm: Handle VIRQ and VFIQ in arm_cpu_do_interrupt_aarch32()
target/arm: Implement DBGVCR32_EL2 system register
hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQ
hw/intc/arm_gic: Add external IRQ lines for VIRQ and VFIQ
target-arm: Expose output GPIO line for VCPU maintenance interrupt
hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU
target-arm: Add ARMCPU fields for GIC CPU i/f config
hw/intc/gicv3: Add defines for ICH system register fields
hw/intc/gicv3: Add data fields for virtualization support
hw/intc/arm_gicv3: Add accessors for ICH_ system registers
hw/intc/arm_gicv3: Implement ICV_ registers which are just accessors
hw/intc/arm_gicv3: Implement ICV_ HPPIR, DIR and RPR registers
hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IAR
hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update()
hw/intc/arm_gicv3: Implement EL2 traps for CPU i/f regs
hw/arm/virt: Support using SMC for PSCI
target/arm/psci.c: If EL2 implemented, start CPUs in EL2
target-arm: Enable EL2 feature bit on A53 and A57
hw/arm/virt: Add board property to enable EL2
Shannon Zhao (1):
arm: virt: Fix segmentation fault when specifying an unsupported CPU
hw/intc/gicv3_internal.h | 79 +++
include/hw/arm/virt.h | 5 +-
include/hw/intc/arm_gic_common.h | 2 +
include/hw/intc/arm_gicv3_common.h | 21 +
include/hw/ssi/aspeed_smc.h | 4 +-
target/arm/cpu.h | 9 +
hw/arm/aspeed.c | 41 ++
hw/arm/imx25_pdk.c | 2 +-
hw/arm/virt-acpi-build.c | 36 +-
hw/arm/virt.c | 88 ++-
hw/arm/xlnx-zynqmp.c | 2 +
hw/block/m25p80.c | 51 +-
hw/i2c/imx_i2c.c | 2 +-
hw/intc/arm_gic_common.c | 6 +
hw/intc/arm_gicv3_common.c | 31 +
hw/intc/arm_gicv3_cpuif.c | 1351 +++++++++++++++++++++++++++++++++++-
hw/ssi/aspeed_smc.c | 330 +++++++--
target/arm/cpu.c | 15 +
target/arm/cpu64.c | 8 +
target/arm/helper.c | 21 +
target/arm/psci.c | 25 +-
tests/m25p80-test.c | 133 ++++
hw/intc/trace-events | 33 +
23 files changed, 2154 insertions(+), 141 deletions(-)
^ permalink raw reply [flat|nested] 13+ messages in thread* [Qemu-devel] [PULL 00/36] target-arm queue
@ 2016-09-22 17:21 Peter Maydell
2016-09-22 19:58 ` no-reply
2016-09-23 9:57 ` Peter Maydell
0 siblings, 2 replies; 13+ messages in thread
From: Peter Maydell @ 2016-09-22 17:21 UTC (permalink / raw)
To: qemu-devel
ARM queue; my to-review pile is not yet empty but since
I have a conference next week I wanted to get the stuff
I had managed to review out.
thanks
-- PMM
The following changes since commit 430da7a81d356e368ccd88dcca60f38da9aa5b9a:
Merge remote-tracking branch 'remotes/riku/tags/pull-linux-user-20160915' into staging (2016-09-22 15:39:54 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160922
for you to fetch changes up to d675765a0244af1d65c292f2508009f1bd13e1b6:
imx: Use 'const char', not 'char const' (2016-09-22 18:13:09 +0100)
----------------------------------------------------------------
target-arm queue:
* add Cortex-A7 CPU
* new ast2500 SoC model and evaluation board
* palmetto-bmc: remove stray double assignment
* aspeed: clean up RAM size handling
* ptimer: framework for defining policy bits to change
behaviour choices for different timer devices
* ptimer: add some test cases
* cadence_gem: add queue support
* loader: support loading images to specified address spaces
* loader: support auto-detect of ELF architecture from file
* dma: xlnx-zynq-devcfg: Fix up XLNX_ZYNQ_DEVCFG_R_MAX
* vmstateify ssd0323
* vmstateify ssi-sd
* disas/arm.c: remove unused macros
* imx: use 'const char', not 'char const'
----------------------------------------------------------------
Alistair Francis (12):
cadence_gem: QOMify Cadence GEM
cadence_gem: Add the num-priority-queues property
cadence_gem: Add support for screening
cadence_gem: Add queue support
cadence_gem: Correct indentation
xlnx-zynqmp: Set the number of priority queues
loader: Allow ELF loader to auto-detect the ELF arch
loader: Use the specified MemoryRegion
loader: Allow a custom AddressSpace when loading ROMs
loader: Add AddressSpace loading support to ELFs
loader: Add AddressSpace loading support to uImages
loader: Add AddressSpace loading support to targphys
Andrey Yurovsky (1):
arm: add Cortex A7 CPU parameters
Cédric Le Goater (14):
ast2400: rename the Aspeed SoC files to aspeed_soc
ast2400: replace ast2400 with aspeed_soc
aspeed-soc: provide a framework to add new SoCs
palmetto-bmc: rename the Aspeed board file to aspeed.c
palmetto-bmc: replace palmetto_bmc with aspeed
palmetto-bmc: add board specific configuration
hw/misc: use macros to define hw-strap1 register on the AST2400 Aspeed SoC
aspeed: add a ast2500 SoC and support to the SCU and SDMC controllers
arm: add support for an ast2500 evaluation board
palmetto-bmc: remove extra no_sdcard assignement
aspeed: calculate the RAM size bits at realize time
aspeed: use error_report instead of LOG_GUEST_ERROR
aspeed: add a ram_size property to the memory controller
aspeed: allocate RAM after the memory controller has checked the size
Dmitry Osipenko (4):
hw/ptimer: Actually stop the timer in case of error
hw/ptimer: Introduce timer policy feature
hw/ptimer: Suppress error messages under qtest
tests: Add ptimer tests
Dr. David Alan Gilbert (2):
vmstateify ssd0323 display
vmstateify ssi-sd
Nathan Rossi (1):
dma: xlnx-zynq-devcfg: Fix up XLNX_ZYNQ_DEVCFG_R_MAX
Peter Maydell (2):
disas/arm.c: Remove unused macro definitions
imx: Use 'const char', not 'char const'
disas/arm.c | 11 -
hw/arm/Makefile.objs | 2 +-
hw/arm/aspeed.c | 197 +++++++++++++
hw/arm/{ast2400.c => aspeed_soc.c} | 131 +++++----
hw/arm/musicpal.c | 2 +-
hw/arm/palmetto-bmc.c | 102 -------
hw/arm/xlnx-zynqmp.c | 2 +
hw/core/loader.c | 89 ++++--
hw/core/ptimer.c | 14 +-
hw/display/ssd0323.c | 102 +++----
hw/dma/xilinx_axidma.c | 2 +-
hw/m68k/mcf5206.c | 2 +-
hw/m68k/mcf5208.c | 2 +-
hw/misc/aspeed_scu.c | 45 ++-
hw/misc/aspeed_sdmc.c | 45 ++-
hw/misc/imx25_ccm.c | 2 +-
hw/misc/imx31_ccm.c | 2 +-
hw/misc/imx6_ccm.c | 4 +-
hw/misc/imx6_src.c | 2 +-
hw/net/cadence_gem.c | 571 +++++++++++++++++++++++++++----------
hw/net/fsl_etsec/etsec.c | 2 +-
hw/net/lan9118.c | 2 +-
hw/sd/ssi-sd.c | 70 ++---
hw/ssi/imx_spi.c | 2 +-
hw/timer/allwinner-a10-pit.c | 2 +-
hw/timer/arm_timer.c | 2 +-
hw/timer/digic-timer.c | 2 +-
hw/timer/etraxfs_timer.c | 6 +-
hw/timer/exynos4210_mct.c | 7 +-
hw/timer/exynos4210_pwm.c | 2 +-
hw/timer/exynos4210_rtc.c | 4 +-
hw/timer/grlib_gptimer.c | 2 +-
hw/timer/imx_epit.c | 6 +-
hw/timer/imx_gpt.c | 4 +-
hw/timer/lm32_timer.c | 2 +-
hw/timer/milkymist-sysctl.c | 4 +-
hw/timer/puv3_ost.c | 2 +-
hw/timer/sh_timer.c | 2 +-
hw/timer/slavio_timer.c | 2 +-
hw/timer/xilinx_timer.c | 2 +-
include/hw/arm/aspeed_soc.h | 59 ++++
include/hw/arm/ast2400.h | 44 ---
include/hw/dma/xlnx-zynq-devcfg.h | 2 +-
include/hw/elf_ops.h | 10 +-
include/hw/loader.h | 73 ++++-
include/hw/misc/aspeed_scu.h | 193 +++++++++++++
include/hw/misc/aspeed_sdmc.h | 2 +
include/hw/net/cadence_gem.h | 19 +-
include/hw/ptimer.h | 25 +-
stubs/vmstate.c | 5 +
target-arm/cpu.c | 46 +++
tests/Makefile.include | 2 +
tests/ptimer-test-stubs.c | 107 +++++++
tests/ptimer-test.c | 568 ++++++++++++++++++++++++++++++++++++
tests/ptimer-test.h | 22 ++
55 files changed, 2084 insertions(+), 549 deletions(-)
create mode 100644 hw/arm/aspeed.c
rename hw/arm/{ast2400.c => aspeed_soc.c} (59%)
delete mode 100644 hw/arm/palmetto-bmc.c
create mode 100644 include/hw/arm/aspeed_soc.h
delete mode 100644 include/hw/arm/ast2400.h
create mode 100644 tests/ptimer-test-stubs.c
create mode 100644 tests/ptimer-test.c
create mode 100644 tests/ptimer-test.h
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [PULL 00/36] target-arm queue
2016-09-22 17:21 Peter Maydell
@ 2016-09-22 19:58 ` no-reply
2016-09-23 9:57 ` Peter Maydell
1 sibling, 0 replies; 13+ messages in thread
From: no-reply @ 2016-09-22 19:58 UTC (permalink / raw)
To: peter.maydell; +Cc: famz, qemu-devel
Hi,
Your series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1474564935-23831-1-git-send-email-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/36] target-arm queue
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git show --no-patch --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/1474564935-23831-1-git-send-email-peter.maydell@linaro.org -> patchew/1474564935-23831-1-git-send-email-peter.maydell@linaro.org
Switched to a new branch 'test'
5968e02 imx: Use 'const char', not 'char const'
1fb0cf3 disas/arm.c: Remove unused macro definitions
f347c98 vmstateify ssi-sd
9f4c6c7 vmstateify ssd0323 display
0e81a82 dma: xlnx-zynq-devcfg: Fix up XLNX_ZYNQ_DEVCFG_R_MAX
a40249e loader: Add AddressSpace loading support to targphys
bd6b978 loader: Add AddressSpace loading support to uImages
79a76bc loader: Add AddressSpace loading support to ELFs
7732745 loader: Allow a custom AddressSpace when loading ROMs
a8295d6 loader: Use the specified MemoryRegion
b9f8718 loader: Allow ELF loader to auto-detect the ELF arch
730e6a6 xlnx-zynqmp: Set the number of priority queues
7c1190d cadence_gem: Correct indentation
f43c4cb cadence_gem: Add queue support
99929ad cadence_gem: Add support for screening
f89652a cadence_gem: Add the num-priority-queues property
19770cb cadence_gem: QOMify Cadence GEM
abb1719 tests: Add ptimer tests
bc870db hw/ptimer: Suppress error messages under qtest
92bbf61 hw/ptimer: Introduce timer policy feature
91bd052 hw/ptimer: Actually stop the timer in case of error
9b990c0 aspeed: allocate RAM after the memory controller has checked the size
f20b9d3 aspeed: add a ram_size property to the memory controller
d8437c9 aspeed: use error_report instead of LOG_GUEST_ERROR
7707c96 aspeed: calculate the RAM size bits at realize time
83c7ed2 palmetto-bmc: remove extra no_sdcard assignement
bfd6c40 arm: add support for an ast2500 evaluation board
1d6d8ff aspeed: add a ast2500 SoC and support to the SCU and SDMC controllers
72d67aa hw/misc: use macros to define hw-strap1 register on the AST2400 Aspeed SoC
74a36a5 palmetto-bmc: add board specific configuration
786f13c palmetto-bmc: replace palmetto_bmc with aspeed
7dfef30 palmetto-bmc: rename the Aspeed board file to aspeed.c
00956c8 aspeed-soc: provide a framework to add new SoCs
aeb8aac ast2400: replace ast2400 with aspeed_soc
910bc01 ast2400: rename the Aspeed SoC files to aspeed_soc
6ad8241 arm: add Cortex A7 CPU parameters
=== OUTPUT BEGIN ===
Checking PATCH 1/36: arm: add Cortex A7 CPU parameters...
Checking PATCH 2/36: ast2400: rename the Aspeed SoC files to aspeed_soc...
Checking PATCH 3/36: ast2400: replace ast2400 with aspeed_soc...
Checking PATCH 4/36: aspeed-soc: provide a framework to add new SoCs...
Checking PATCH 5/36: palmetto-bmc: rename the Aspeed board file to aspeed.c...
Checking PATCH 6/36: palmetto-bmc: replace palmetto_bmc with aspeed...
Checking PATCH 7/36: palmetto-bmc: add board specific configuration...
Checking PATCH 8/36: hw/misc: use macros to define hw-strap1 register on the AST2400 Aspeed SoC...
Checking PATCH 9/36: aspeed: add a ast2500 SoC and support to the SCU and SDMC controllers...
Checking PATCH 10/36: arm: add support for an ast2500 evaluation board...
Checking PATCH 11/36: palmetto-bmc: remove extra no_sdcard assignement...
Checking PATCH 12/36: aspeed: calculate the RAM size bits at realize time...
Checking PATCH 13/36: aspeed: use error_report instead of LOG_GUEST_ERROR...
Checking PATCH 14/36: aspeed: add a ram_size property to the memory controller...
Checking PATCH 15/36: aspeed: allocate RAM after the memory controller has checked the size...
Checking PATCH 16/36: hw/ptimer: Actually stop the timer in case of error...
Checking PATCH 17/36: hw/ptimer: Introduce timer policy feature...
Checking PATCH 18/36: hw/ptimer: Suppress error messages under qtest...
Checking PATCH 19/36: tests: Add ptimer tests...
WARNING: line over 80 characters
#694: FILE: tests/ptimer-test.c:525:
+ g_strdup_printf("/ptimer/on_the_fly_mode_change policy=%s", policy_name),
WARNING: line over 80 characters
#698: FILE: tests/ptimer-test.c:529:
+ g_strdup_printf("/ptimer/on_the_fly_period_change policy=%s", policy_name),
WARNING: line over 80 characters
#702: FILE: tests/ptimer-test.c:533:
+ g_strdup_printf("/ptimer/on_the_fly_freq_change policy=%s", policy_name),
total: 0 errors, 3 warnings, 722 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 20/36: cadence_gem: QOMify Cadence GEM...
Checking PATCH 21/36: cadence_gem: Add the num-priority-queues property...
Checking PATCH 22/36: cadence_gem: Add support for screening...
Checking PATCH 23/36: cadence_gem: Add queue support...
ERROR: suspect code indent for conditional statements (4, 4)
#154: FILE: hw/net/cadence_gem.c:1056:
+ for (q = s->num_priority_queues - 1; q >= 0; q--) {
/* read current descriptor */
total: 1 errors, 0 warnings, 285 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 24/36: cadence_gem: Correct indentation...
Checking PATCH 25/36: xlnx-zynqmp: Set the number of priority queues...
Checking PATCH 26/36: loader: Allow ELF loader to auto-detect the ELF arch...
Checking PATCH 27/36: loader: Use the specified MemoryRegion...
Checking PATCH 28/36: loader: Allow a custom AddressSpace when loading ROMs...
Checking PATCH 29/36: loader: Add AddressSpace loading support to ELFs...
Checking PATCH 30/36: loader: Add AddressSpace loading support to uImages...
Checking PATCH 31/36: loader: Add AddressSpace loading support to targphys...
Checking PATCH 32/36: dma: xlnx-zynq-devcfg: Fix up XLNX_ZYNQ_DEVCFG_R_MAX...
Checking PATCH 33/36: vmstateify ssd0323 display...
Checking PATCH 34/36: vmstateify ssi-sd...
Checking PATCH 35/36: disas/arm.c: Remove unused macro definitions...
Checking PATCH 36/36: imx: Use 'const char', not 'char const'...
=== OUTPUT END ===
Test command exited with code: 1
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [PULL 00/36] target-arm queue
2016-09-22 17:21 Peter Maydell
2016-09-22 19:58 ` no-reply
@ 2016-09-23 9:57 ` Peter Maydell
1 sibling, 0 replies; 13+ messages in thread
From: Peter Maydell @ 2016-09-23 9:57 UTC (permalink / raw)
To: QEMU Developers
On 22 September 2016 at 18:21, Peter Maydell <peter.maydell@linaro.org> wrote:
> ARM queue; my to-review pile is not yet empty but since
> I have a conference next week I wanted to get the stuff
> I had managed to review out.
>
> thanks
> -- PMM
>
> The following changes since commit 430da7a81d356e368ccd88dcca60f38da9aa5b9a:
>
> Merge remote-tracking branch 'remotes/riku/tags/pull-linux-user-20160915' into staging (2016-09-22 15:39:54 +0100)
>
> are available in the git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160922
>
> for you to fetch changes up to d675765a0244af1d65c292f2508009f1bd13e1b6:
>
> imx: Use 'const char', not 'char const' (2016-09-22 18:13:09 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * add Cortex-A7 CPU
> * new ast2500 SoC model and evaluation board
> * palmetto-bmc: remove stray double assignment
> * aspeed: clean up RAM size handling
> * ptimer: framework for defining policy bits to change
> behaviour choices for different timer devices
> * ptimer: add some test cases
> * cadence_gem: add queue support
> * loader: support loading images to specified address spaces
> * loader: support auto-detect of ELF architecture from file
> * dma: xlnx-zynq-devcfg: Fix up XLNX_ZYNQ_DEVCFG_R_MAX
> * vmstateify ssd0323
> * vmstateify ssi-sd
> * disas/arm.c: remove unused macros
> * imx: use 'const char', not 'char const'
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Qemu-devel] [PULL 00/36] target-arm queue
@ 2016-02-18 14:34 Peter Maydell
2016-02-18 15:19 ` Peter Maydell
0 siblings, 1 reply; 13+ messages in thread
From: Peter Maydell @ 2016-02-18 14:34 UTC (permalink / raw)
To: qemu-devel
ARM pullreq with a whole pile of stuff; QOMification of SD cards
is perhaps the biggest individual thing here.
thanks
-- PMM
The following changes since commit 339b665c883b209982fa161dc090ffaf242ab12b:
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.6-20160218' into staging (2016-02-18 10:29:47 +0000)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160218
for you to fetch changes up to ee24ff5593b6f88c693af1b11e5af095ed7c4696:
hw/timer: QOM'ify pxa2xx_timer (2016-02-18 14:26:33 +0000)
----------------------------------------------------------------
target-arm queue:
* implement or fix various EL3 trap behaviour for system registers
* clean up the trap/undef handling of the SRS instruction
* add some missing AArch64 performance monitor system registers
* implement reset for the PL061 GPIO device
* QOMify sd.c and the pxa2xx_mmci device
* SD card emulation fixes for booting Tianocore UEFI on RPi2
* QOMify various ARM timer devices
----------------------------------------------------------------
Alistair Francis (3):
target-arm: Add the pmceid0 and pmceid1 registers
target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers
target-arm: Add PMUSERENR_EL0 register
Andrew Baumann (3):
hw/sd: implement CMD23 (SET_BLOCK_COUNT) for MMC compatibility
hw/sd: model a power-up delay, as a workaround for an EDK2 bug
hw/sd: use guest error logging rather than fprintf to stderr
Peter Maydell (21):
target-arm: correct CNTFRQ access rights
target-arm: Fix handling of SCR.SMD
target-arm: Implement MDCR_EL3.TDOSA and MDCR_EL2.TDOSA traps
target-arm: Implement MDCR_EL2.TDRA traps
target-arm: Implement MDCR_EL3.TDA and MDCR_EL2.TDA traps
target-arm: Report correct syndrome for FPEXC32_EL2 traps
target-arm: Clean up trap/undef handling of SRS
target-arm: Move get/set_r13_banked() to op_helper.c
target-arm: Move bank_number() into internals.h
target-arm: Combine user-only and softmmu get/set_r13_banked()
target-arm: UNDEF in the UNPREDICTABLE SRS-from-System case
hw/sd/sdhci.c: Remove x-drive property
hw/sd/sd.c: QOMify
hw/sd/sd.c: Convert sd_reset() function into Device reset method
hw/sd: Add QOM bus which SD cards plug in to
hw/sd/sdhci.c: Update to use SDBus APIs
sdhci_sysbus: Create SD card device in users, not the device itself
hw/sd/pxa2xx_mmci: convert to SysBusDevice object
hw/sd/pxa2xx_mmci: Update to use new SDBus APIs
hw/sd/pxa2xx_mmci: Convert to VMStateDescription
hw/sd/pxa2xx_mmci: Add reset function
Wei Huang (2):
ARM: PL061: Clear PL061 device state after reset
ARM: PL061: Cleaning field of PL061 device state
xiaoqiang.zhao (7):
hw/timer: QOM'ify arm_timer (pass 1)
hw/timer: QOM'ify arm_timer (pass 2)
hw/timer: QOM'ify exynos4210_mct
hw/timer: QOM'ify exynos4210_pwm
hw/timer: QOM'ify exynos4210_rtc
hw/timer: QOM'ify pl031
hw/timer: QOM'ify pxa2xx_timer
hw/arm/xilinx_zynq.c | 17 ++-
hw/arm/xlnx-ep108.c | 21 ++++
hw/arm/xlnx-zynqmp.c | 8 ++
hw/gpio/pl061.c | 37 ++++--
hw/sd/Makefile.objs | 2 +-
hw/sd/core.c | 146 ++++++++++++++++++++++
hw/sd/pxa2xx_mmci.c | 306 ++++++++++++++++++++++++++++++----------------
hw/sd/sd.c | 289 ++++++++++++++++++++++++++++++++++++-------
hw/sd/sdhci.c | 82 +++++++------
hw/timer/arm_timer.c | 42 +++----
hw/timer/exynos4210_mct.c | 12 +-
hw/timer/exynos4210_pwm.c | 12 +-
hw/timer/exynos4210_rtc.c | 12 +-
hw/timer/pl031.c | 11 +-
hw/timer/pxa2xx_timer.c | 36 +++---
include/hw/sd/sd.h | 65 ++++++++++
include/hw/sd/sdhci.h | 3 +-
target-arm/cpu-qom.h | 2 +
target-arm/cpu.c | 2 +
target-arm/cpu.h | 29 +++++
target-arm/cpu64.c | 2 +
target-arm/helper.c | 214 ++++++++++++++++++++------------
target-arm/internals.h | 26 +++-
target-arm/op_helper.c | 51 +++++++-
target-arm/translate.c | 67 +++++++++-
25 files changed, 1145 insertions(+), 349 deletions(-)
create mode 100644 hw/sd/core.c
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [PULL 00/36] target-arm queue
2016-02-18 14:34 Peter Maydell
@ 2016-02-18 15:19 ` Peter Maydell
0 siblings, 0 replies; 13+ messages in thread
From: Peter Maydell @ 2016-02-18 15:19 UTC (permalink / raw)
To: QEMU Developers
On 18 February 2016 at 14:34, Peter Maydell <peter.maydell@linaro.org> wrote:
> ARM pullreq with a whole pile of stuff; QOMification of SD cards
> is perhaps the biggest individual thing here.
>
> thanks
> -- PMM
>
> The following changes since commit 339b665c883b209982fa161dc090ffaf242ab12b:
>
> Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.6-20160218' into staging (2016-02-18 10:29:47 +0000)
>
> are available in the git repository at:
>
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160218
Minor fixup needed for the w32 compiler that doesn't like duplicate
typedefs, to the "hw/sd/pxa2xx_mmci: convert to SysBusDevice object"
patch:
diff --git a/hw/sd/pxa2xx_mmci.c b/hw/sd/pxa2xx_mmci.c
index cadbba3..e3753e5 100644
--- a/hw/sd/pxa2xx_mmci.c
+++ b/hw/sd/pxa2xx_mmci.c
@@ -21,7 +21,7 @@
#define TYPE_PXA2XX_MMCI "pxa2xx-mmci"
#define PXA2XX_MMCI(obj) OBJECT_CHECK(PXA2xxMMCIState, (obj), TYPE_PXA2XX_MMCI)
-typedef struct PXA2xxMMCIState {
+struct PXA2xxMMCIState {
SysBusDevice parent_obj;
MemoryRegion iomem;
@@ -57,7 +57,7 @@ typedef struct PXA2xxMMCIState {
int resp_len;
int cmdreq;
-} PXA2xxMMCIState;
+};
#define MMC_STRPCL 0x00 /* MMC Clock Start/Stop register */
#define MMC_STAT 0x04 /* MMC Status register */
New cover letter coming up shortly.
-- PMM
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Qemu-devel] [PULL 00/36] target-arm queue
@ 2016-01-21 14:55 Peter Maydell
2016-01-21 15:53 ` Peter Maydell
0 siblings, 1 reply; 13+ messages in thread
From: Peter Maydell @ 2016-01-21 14:55 UTC (permalink / raw)
To: qemu-devel
The biggie here is the multi-ases support and corresponding TrustZone
support code. There are also a bunch of other comparatively minor
things...
thanks
-- PMM
The following changes since commit 3c9331c47f22224118d5019b0af8eac704824d8d:
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2016-01-21 13:09:47 +0000)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160121
for you to fetch changes up to 03fbf20f4da58f41998dc10ec7542f65d37ba759:
target-arm: Implement FPEXC32_EL2 system register (2016-01-21 14:15:09 +0000)
----------------------------------------------------------------
target-arm queue:
* connect SPI devices in Xilinx Zynq platforms
* multiple-address-space support
* use multiple-address-space support for ARM TrustZone
* arm_gic: return correct ID registers for 11MPCore/v1/v2 GICs
* various fixes for (currently disabled) AArch64 EL2 and EL3 support
* add 'always-on' property to the virt board timer DT entry
----------------------------------------------------------------
Alistair Francis (6):
m25p80.c: Add sst25wf080 SPI flash device
ssi: Move ssi.h into a separate directory
xilinx_spips: Separate the state struct into a header
xlnx-zynqmp: Connect the SPI devices
xlnx-ep108: Connect the SPI Flash
arm_gic: Update ID registers based on revision
Christoffer Dall (1):
hw/arm/virt: Add always-on property to the virt board timer
Peter Crosthwaite (4):
qdev: get_child_bus(): Use QOM lookup if available
misc: zynq-xadc: Fix off-by-one
memory: Add address_space_init_shareable()
qom/cpu: Add MemoryRegion property
Peter Maydell (25):
exec.c: Don't set cpu->as until cpu_address_space_init
exec.c: Allow target CPUs to define multiple AddressSpaces
exec-all.h: Document tlb_set_page_with_attrs, tlb_set_page
cpu: Add new get_phys_page_attrs_debug() method
cpu: Add new asidx_from_attrs() method
cputlb.c: Use correct address space when looking up MemoryRegionSection
exec.c: Pass MemTxAttrs to iotlb_to_region so it uses the right AS
exec.c: Add cpu_get_address_space()
exec.c: Use cpu_get_phys_page_attrs_debug
exec.c: Use correct AddressSpace in watch_mem_read and watch_mem_write
target-arm: Add QOM property for Secure memory region
target-arm: Implement asidx_from_attrs
target-arm: Implement cpu_get_phys_page_attrs_debug
target-arm: Support multiple address spaces in page table walks
hw/arm/virt: Wire up memory region to CPUs explicitly
hw/arm/virt: add secure memory region and UART
target-arm: Properly support EL2 and EL3 in arm_el_is_aa64()
target-arm: Move aarch64_cpu_do_interrupt() to helper.c
target-arm: Use a single entry point for AArch64 and AArch32 exceptions
target-arm: Pull semihosting handling out to arm_cpu_do_interrupt()
target-arm: Fix wrong AArch64 entry offset for EL2/EL3 target
target-arm: Handle exception return from AArch64 to non-EL0 AArch32
target-arm: Implement remaining illegal return event checks
target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM mode
target-arm: Implement FPEXC32_EL2 system register
cpus.c | 13 +-
cputlb.c | 9 +-
exec.c | 103 ++++++++----
hw/arm/pxa2xx.c | 2 +-
hw/arm/spitz.c | 2 +-
hw/arm/stellaris.c | 2 +-
hw/arm/strongarm.c | 2 +-
hw/arm/tosa.c | 2 +-
hw/arm/virt.c | 59 ++++++-
hw/arm/xilinx_zynq.c | 2 +-
hw/arm/xlnx-ep108.c | 16 ++
hw/arm/xlnx-zynqmp.c | 31 ++++
hw/arm/z2.c | 2 +-
hw/block/m25p80.c | 3 +-
hw/core/qdev.c | 6 +
hw/display/ads7846.c | 2 +-
hw/display/ssd0323.c | 2 +-
hw/intc/arm_gic.c | 35 ++++-
hw/microblaze/petalogix_ml605_mmu.c | 2 +-
hw/misc/max111x.c | 2 +-
hw/misc/zynq-xadc.c | 2 +-
hw/sd/ssi-sd.c | 2 +-
hw/ssi/pl022.c | 2 +-
hw/ssi/ssi.c | 2 +-
hw/ssi/xilinx_spi.c | 2 +-
hw/ssi/xilinx_spips.c | 48 +-----
include/exec/exec-all.h | 69 ++++++++-
include/exec/memory.h | 18 +++
include/hw/arm/virt.h | 1 +
include/hw/arm/xlnx-zynqmp.h | 3 +
include/hw/{ => ssi}/ssi.h | 10 +-
include/hw/ssi/xilinx_spips.h | 72 +++++++++
include/qom/cpu.h | 57 ++++++-
memory.c | 27 ++++
softmmu_template.h | 4 +-
target-arm/cpu-qom.h | 8 +-
target-arm/cpu.c | 35 ++++-
target-arm/cpu.h | 56 +++++--
target-arm/cpu64.c | 3 -
target-arm/helper-a64.c | 104 -------------
target-arm/helper.c | 301 +++++++++++++++++++++++++++++-------
target-arm/op_helper.c | 94 ++++++++---
target-i386/cpu.c | 7 +-
43 files changed, 909 insertions(+), 315 deletions(-)
rename include/hw/{ => ssi}/ssi.h (96%)
create mode 100644 include/hw/ssi/xilinx_spips.h
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [PULL 00/36] target-arm queue
2016-01-21 14:55 Peter Maydell
@ 2016-01-21 15:53 ` Peter Maydell
0 siblings, 0 replies; 13+ messages in thread
From: Peter Maydell @ 2016-01-21 15:53 UTC (permalink / raw)
To: QEMU Developers
On 21 January 2016 at 14:55, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> The biggie here is the multi-ases support and corresponding TrustZone
> support code. There are also a bunch of other comparatively minor
> things...
>
> thanks
> -- PMM
>
> The following changes since commit 3c9331c47f22224118d5019b0af8eac704824d8d:
>
> Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2016-01-21 13:09:47 +0000)
>
> are available in the git repository at:
>
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20160121
>
> for you to fetch changes up to 03fbf20f4da58f41998dc10ec7542f65d37ba759:
>
> target-arm: Implement FPEXC32_EL2 system register (2016-01-21 14:15:09 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * connect SPI devices in Xilinx Zynq platforms
> * multiple-address-space support
> * use multiple-address-space support for ARM TrustZone
> * arm_gic: return correct ID registers for 11MPCore/v1/v2 GICs
> * various fixes for (currently disabled) AArch64 EL2 and EL3 support
> * add 'always-on' property to the virt board timer DT entry
>
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2017-09-04 16:20 UTC | newest]
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