From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58041) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aWZt6-0004jO-Ap for qemu-devel@nongnu.org; Thu, 18 Feb 2016 20:29:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aWZt3-0000HV-1B for qemu-devel@nongnu.org; Thu, 18 Feb 2016 20:29:40 -0500 Received: from gateway0.eecs.berkeley.edu ([169.229.60.87]:37994) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aWZt2-0000HC-3o for qemu-devel@nongnu.org; Thu, 18 Feb 2016 20:29:36 -0500 From: Sagar Karandikar Date: Thu, 18 Feb 2016 17:02:04 -0800 Message-Id: <1455843725-88869-1-git-send-email-sagark@eecs.berkeley.edu> Subject: [Qemu-devel] [RFC 0/1] riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Sagar Karandikar , stefanha@redhat.com, rth@twiddle.net The patch in this RFC adds support for the RISC-V ISA [1] as a target. It has been tested booting Linux and FreeBSD, passes the RISC-V assembly test suite, and has had the riscv-torture tester running on it for a couple of weeks now without any issues arising. With this RFC, I mainly wanted to get input on the overall design of the target implementation, as well as see if any regular contributors would be interested in co-mentoring RISC-V related projects for QEMU's Google Summer of Code with me. In case anyone wants to test it out, there is a repo on the RISC-V GitHub organization with a README.md containing instructions, a copy of the full v2.5.0 codebase with this patch applied, and links to prebuilt RISC-V linux images [2]. Some notes/questions: - This provides support only for the 64-bit version of the ISA and full system emulation (no user-mode) - This currently applies to the 2.5.0 release version. I will bump the underlying codebase, split this into multiple patches, apply style checks before submitting real patches - The code in target-riscv/fpu-custom-riscv is an updated/modified version of softfloat. Is it okay to submodule this until the FPU behavior in RISC-V is stabilized? (and then later, presumably merge it with the version of softfloat included in QEMU). For current review purposes, I believe everything in this directory can be ignored. - The devices in hw/riscv/htif are intended to mimic the experimental devices that we use with our RISC-V test chips. These will be removed and replaced with "real" devices once there is better software support in the OS/bootloader ports. Potentially useful references: - RISC-V User Spec: See [3]. This spec is frozen. - RISC-V Privileged Spec: See [4]. This spec is a draft. - Spike, the reference simulator for the ISA: See [5]. [1] https://riscv.org [2] https://github.com/riscv/riscv-qemu [3] http://riscv.org/wp-content/uploads/2015/11/riscv-spec-v2.0.pdf [4] http://riscv.org/wp-content/uploads/2015/11/riscv-privileged-spec-v1.7.pdf [5] https://github.com/riscv/riscv-isa-sim Sagar Karandikar (1): riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G) arch_init.c | 2 + configure | 13 + cpus.c | 6 + default-configs/riscv-linux-user.mak | 1 + default-configs/riscv-softmmu.mak | 38 + disas.c | 2 + disas/Makefile.objs | 1 + disas/riscv.c | 46 + hw/riscv/Makefile.objs | 5 + hw/riscv/cputimer.c | 170 ++ hw/riscv/htif/frontend.c | 215 ++ hw/riscv/htif/htif.c | 459 +++++ hw/riscv/riscv_board.c | 330 +++ hw/riscv/riscv_int.c | 84 + hw/riscv/softint.c | 121 ++ include/disas/bfd.h | 1 + include/elf.h | 2 + include/exec/poison.h | 1 + include/exec/user/thunk.h | 2 +- include/hw/riscv/bios.h | 4 + include/hw/riscv/cpudevs.h | 14 + include/hw/riscv/cputimer.h | 4 + include/hw/riscv/htif/frontend.h | 30 + include/hw/riscv/htif/htif.h | 76 + include/hw/riscv/riscv.h | 10 + include/hw/riscv/softint.h | 50 + include/sysemu/arch_init.h | 1 + target-riscv/Makefile.objs | 114 ++ target-riscv/TODO | 17 + target-riscv/cpu-qom.h | 86 + target-riscv/cpu.c | 143 ++ target-riscv/cpu.h | 449 ++++ .../fpu-custom-riscv/8086/OLD-specialize.c | 40 + .../fpu-custom-riscv/8086/OLD-specialize.h | 379 ++++ target-riscv/fpu-custom-riscv/8086/platform.h | 38 + .../fpu-custom-riscv/8086/s_commonNaNToF32UI.c | 17 + .../fpu-custom-riscv/8086/s_commonNaNToF64UI.c | 19 + .../fpu-custom-riscv/8086/s_f32UIToCommonNaN.c | 25 + .../fpu-custom-riscv/8086/s_f64UIToCommonNaN.c | 25 + .../fpu-custom-riscv/8086/s_isSigNaNF32UI.c | 13 + .../fpu-custom-riscv/8086/s_isSigNaNF64UI.c | 15 + .../fpu-custom-riscv/8086/s_propagateNaNF32UI.c | 55 + .../fpu-custom-riscv/8086/s_propagateNaNF64UI.c | 55 + .../fpu-custom-riscv/8086/softfloat_raiseFlags.c | 51 + .../fpu-custom-riscv/8086/softfloat_types.h | 16 + target-riscv/fpu-custom-riscv/8086/specialize.h | 113 + target-riscv/fpu-custom-riscv/f32_add.c | 29 + target-riscv/fpu-custom-riscv/f32_classify.c | 33 + target-riscv/fpu-custom-riscv/f32_div.c | 96 + target-riscv/fpu-custom-riscv/f32_eq.c | 34 + target-riscv/fpu-custom-riscv/f32_eq_signaling.c | 29 + target-riscv/fpu-custom-riscv/f32_isSignalingNaN.c | 16 + target-riscv/fpu-custom-riscv/f32_le.c | 34 + target-riscv/fpu-custom-riscv/f32_le_quiet.c | 39 + target-riscv/fpu-custom-riscv/f32_lt.c | 34 + target-riscv/fpu-custom-riscv/f32_lt_quiet.c | 39 + target-riscv/fpu-custom-riscv/f32_mul.c | 89 + target-riscv/fpu-custom-riscv/f32_mulAdd.c | 25 + target-riscv/fpu-custom-riscv/f32_rem.c | 124 ++ target-riscv/fpu-custom-riscv/f32_roundToInt.c | 78 + target-riscv/fpu-custom-riscv/f32_sqrt.c | 74 + target-riscv/fpu-custom-riscv/f32_sub.c | 29 + target-riscv/fpu-custom-riscv/f32_to_f64.c | 47 + target-riscv/fpu-custom-riscv/f32_to_i32.c | 34 + .../fpu-custom-riscv/f32_to_i32_r_minMag.c | 45 + target-riscv/fpu-custom-riscv/f32_to_i64.c | 44 + .../fpu-custom-riscv/f32_to_i64_r_minMag.c | 52 + target-riscv/fpu-custom-riscv/f32_to_ui32.c | 33 + .../fpu-custom-riscv/f32_to_ui32_r_minMag.c | 41 + target-riscv/fpu-custom-riscv/f32_to_ui64.c | 42 + .../fpu-custom-riscv/f32_to_ui64_r_minMag.c | 45 + target-riscv/fpu-custom-riscv/f64_add.c | 29 + target-riscv/fpu-custom-riscv/f64_classify.c | 33 + target-riscv/fpu-custom-riscv/f64_div.c | 104 + target-riscv/fpu-custom-riscv/f64_eq.c | 35 + target-riscv/fpu-custom-riscv/f64_eq_signaling.c | 30 + target-riscv/fpu-custom-riscv/f64_isSignalingNaN.c | 16 + target-riscv/fpu-custom-riscv/f64_le.c | 35 + target-riscv/fpu-custom-riscv/f64_le_quiet.c | 40 + target-riscv/fpu-custom-riscv/f64_lt.c | 35 + target-riscv/fpu-custom-riscv/f64_lt_quiet.c | 40 + target-riscv/fpu-custom-riscv/f64_mul.c | 91 + target-riscv/fpu-custom-riscv/f64_mulAdd.c | 25 + target-riscv/fpu-custom-riscv/f64_rem.c | 113 + target-riscv/fpu-custom-riscv/f64_roundToInt.c | 80 + target-riscv/fpu-custom-riscv/f64_sqrt.c | 74 + target-riscv/fpu-custom-riscv/f64_sub.c | 29 + target-riscv/fpu-custom-riscv/f64_to_f32.c | 43 + target-riscv/fpu-custom-riscv/f64_to_i32.c | 30 + .../fpu-custom-riscv/f64_to_i32_r_minMag.c | 50 + target-riscv/fpu-custom-riscv/f64_to_i64.c | 46 + .../fpu-custom-riscv/f64_to_i64_r_minMag.c | 52 + target-riscv/fpu-custom-riscv/f64_to_ui32.c | 29 + .../fpu-custom-riscv/f64_to_ui32_r_minMag.c | 40 + target-riscv/fpu-custom-riscv/f64_to_ui64.c | 41 + .../fpu-custom-riscv/f64_to_ui64_r_minMag.c | 45 + target-riscv/fpu-custom-riscv/i32_to_f32.c | 21 + target-riscv/fpu-custom-riscv/i32_to_f64.c | 31 + target-riscv/fpu-custom-riscv/i64_to_f32.c | 36 + target-riscv/fpu-custom-riscv/i64_to_f64.c | 21 + target-riscv/fpu-custom-riscv/internals.h | 232 +++ target-riscv/fpu-custom-riscv/platform.h | 42 + target-riscv/fpu-custom-riscv/primitives.h | 628 ++++++ target-riscv/fpu-custom-riscv/s_add128.c | 17 + target-riscv/fpu-custom-riscv/s_add192.c | 30 + target-riscv/fpu-custom-riscv/s_addMagsF32.c | 75 + target-riscv/fpu-custom-riscv/s_addMagsF64.c | 77 + target-riscv/fpu-custom-riscv/s_commonNaNToF32UI.c | 17 + target-riscv/fpu-custom-riscv/s_commonNaNToF64UI.c | 17 + .../fpu-custom-riscv/s_countLeadingZeros32.c | 22 + .../fpu-custom-riscv/s_countLeadingZeros64.c | 32 + .../fpu-custom-riscv/s_countLeadingZeros8.c | 24 + target-riscv/fpu-custom-riscv/s_eq128.c | 13 + .../fpu-custom-riscv/s_estimateDiv128To64.c | 28 + target-riscv/fpu-custom-riscv/s_estimateSqrt32.c | 37 + target-riscv/fpu-custom-riscv/s_f32UIToCommonNaN.c | 25 + target-riscv/fpu-custom-riscv/s_f64UIToCommonNaN.c | 25 + target-riscv/fpu-custom-riscv/s_isSigNaNF32UI.c | 13 + target-riscv/fpu-custom-riscv/s_isSigNaNF64UI.c | 15 + target-riscv/fpu-custom-riscv/s_le128.c | 13 + target-riscv/fpu-custom-riscv/s_lt128.c | 13 + target-riscv/fpu-custom-riscv/s_mul128By64To192.c | 20 + target-riscv/fpu-custom-riscv/s_mul128To256.c | 28 + target-riscv/fpu-custom-riscv/s_mul64To128.c | 28 + target-riscv/fpu-custom-riscv/s_mulAddF32.c | 171 ++ target-riscv/fpu-custom-riscv/s_mulAddF64.c | 188 ++ .../fpu-custom-riscv/s_normRoundPackToF32.c | 24 + .../fpu-custom-riscv/s_normRoundPackToF64.c | 24 + .../fpu-custom-riscv/s_normSubnormalF32Sig.c | 18 + .../fpu-custom-riscv/s_normSubnormalF64Sig.c | 18 + .../fpu-custom-riscv/s_propagateNaNF32UI.c | 25 + .../fpu-custom-riscv/s_propagateNaNF64UI.c | 25 + target-riscv/fpu-custom-riscv/s_roundPackToF32.c | 65 + target-riscv/fpu-custom-riscv/s_roundPackToF64.c | 66 + target-riscv/fpu-custom-riscv/s_roundPackToI32.c | 48 + target-riscv/fpu-custom-riscv/s_roundPackToI64.c | 52 + target-riscv/fpu-custom-riscv/s_roundPackToUI32.c | 44 + target-riscv/fpu-custom-riscv/s_roundPackToUI64.c | 46 + .../fpu-custom-riscv/s_shift128ExtraRightJam.c | 38 + target-riscv/fpu-custom-riscv/s_shift128RightJam.c | 31 + target-riscv/fpu-custom-riscv/s_shift32RightJam.c | 15 + .../fpu-custom-riscv/s_shift64ExtraRightJam.c | 23 + target-riscv/fpu-custom-riscv/s_shift64RightJam.c | 15 + .../s_shortShift128ExtraRightJam.c | 20 + .../fpu-custom-riscv/s_shortShift128Left.c | 16 + .../fpu-custom-riscv/s_shortShift128Right.c | 16 + .../fpu-custom-riscv/s_shortShift192Left.c | 20 + .../fpu-custom-riscv/s_shortShift32Right1Jam.c | 12 + .../fpu-custom-riscv/s_shortShift64ExtraRightJam.c | 17 + .../fpu-custom-riscv/s_shortShift64RightJam.c | 12 + target-riscv/fpu-custom-riscv/s_sub128.c | 17 + target-riscv/fpu-custom-riscv/s_sub192.c | 30 + target-riscv/fpu-custom-riscv/s_subMagsF32.c | 81 + target-riscv/fpu-custom-riscv/s_subMagsF64.c | 81 + target-riscv/fpu-custom-riscv/softfloat.ac | 0 target-riscv/fpu-custom-riscv/softfloat.h | 235 +++ target-riscv/fpu-custom-riscv/softfloat.mk.in | 126 ++ .../fpu-custom-riscv/softfloat_raiseFlags.c | 51 + target-riscv/fpu-custom-riscv/softfloat_state.c | 19 + target-riscv/fpu-custom-riscv/softfloat_types.h | 16 + target-riscv/fpu-custom-riscv/specialize.h | 113 + target-riscv/fpu-custom-riscv/ui32_to_f32.c | 25 + target-riscv/fpu-custom-riscv/ui32_to_f64.c | 26 + target-riscv/fpu-custom-riscv/ui64_to_f32.c | 31 + target-riscv/fpu-custom-riscv/ui64_to_f64.c | 25 + target-riscv/gdbstub.c | 177 ++ target-riscv/helper.c | 356 ++++ target-riscv/helper.h | 82 + target-riscv/instmap.h | 311 +++ target-riscv/machine.c | 91 + target-riscv/op_helper.c | 1037 ++++++++++ target-riscv/riscv-defs.h | 14 + target-riscv/translate.c | 2155 ++++++++++++++++++++ target-riscv/translate_init.c | 63 + 174 files changed, 13518 insertions(+), 1 deletion(-) create mode 100644 default-configs/riscv-linux-user.mak create mode 100644 default-configs/riscv-softmmu.mak create mode 100644 disas/riscv.c create mode 100644 hw/riscv/Makefile.objs create mode 100644 hw/riscv/cputimer.c create mode 100644 hw/riscv/htif/frontend.c create mode 100644 hw/riscv/htif/htif.c create mode 100644 hw/riscv/riscv_board.c create mode 100644 hw/riscv/riscv_int.c create mode 100644 hw/riscv/softint.c create mode 100644 include/hw/riscv/bios.h create mode 100644 include/hw/riscv/cpudevs.h create mode 100644 include/hw/riscv/cputimer.h create mode 100644 include/hw/riscv/htif/frontend.h create mode 100644 include/hw/riscv/htif/htif.h create mode 100644 include/hw/riscv/riscv.h create mode 100644 include/hw/riscv/softint.h create mode 100644 target-riscv/Makefile.objs create mode 100644 target-riscv/TODO create mode 100644 target-riscv/cpu-qom.h create mode 100644 target-riscv/cpu.c create mode 100644 target-riscv/cpu.h create mode 100755 target-riscv/fpu-custom-riscv/8086/OLD-specialize.c create mode 100755 target-riscv/fpu-custom-riscv/8086/OLD-specialize.h create mode 100755 target-riscv/fpu-custom-riscv/8086/platform.h create mode 100755 target-riscv/fpu-custom-riscv/8086/s_commonNaNToF32UI.c create mode 100755 target-riscv/fpu-custom-riscv/8086/s_commonNaNToF64UI.c create mode 100755 target-riscv/fpu-custom-riscv/8086/s_f32UIToCommonNaN.c create mode 100755 target-riscv/fpu-custom-riscv/8086/s_f64UIToCommonNaN.c create mode 100755 target-riscv/fpu-custom-riscv/8086/s_isSigNaNF32UI.c create mode 100755 target-riscv/fpu-custom-riscv/8086/s_isSigNaNF64UI.c create mode 100755 target-riscv/fpu-custom-riscv/8086/s_propagateNaNF32UI.c create mode 100755 target-riscv/fpu-custom-riscv/8086/s_propagateNaNF64UI.c create mode 100755 target-riscv/fpu-custom-riscv/8086/softfloat_raiseFlags.c create mode 100755 target-riscv/fpu-custom-riscv/8086/softfloat_types.h create mode 100755 target-riscv/fpu-custom-riscv/8086/specialize.h create mode 100755 target-riscv/fpu-custom-riscv/f32_add.c create mode 100755 target-riscv/fpu-custom-riscv/f32_classify.c create mode 100755 target-riscv/fpu-custom-riscv/f32_div.c create mode 100755 target-riscv/fpu-custom-riscv/f32_eq.c create mode 100755 target-riscv/fpu-custom-riscv/f32_eq_signaling.c create mode 100755 target-riscv/fpu-custom-riscv/f32_isSignalingNaN.c create mode 100755 target-riscv/fpu-custom-riscv/f32_le.c create mode 100755 target-riscv/fpu-custom-riscv/f32_le_quiet.c create mode 100755 target-riscv/fpu-custom-riscv/f32_lt.c create mode 100755 target-riscv/fpu-custom-riscv/f32_lt_quiet.c create mode 100755 target-riscv/fpu-custom-riscv/f32_mul.c create mode 100755 target-riscv/fpu-custom-riscv/f32_mulAdd.c create mode 100755 target-riscv/fpu-custom-riscv/f32_rem.c create mode 100755 target-riscv/fpu-custom-riscv/f32_roundToInt.c create mode 100755 target-riscv/fpu-custom-riscv/f32_sqrt.c create mode 100755 target-riscv/fpu-custom-riscv/f32_sub.c create mode 100755 target-riscv/fpu-custom-riscv/f32_to_f64.c create mode 100755 target-riscv/fpu-custom-riscv/f32_to_i32.c create mode 100755 target-riscv/fpu-custom-riscv/f32_to_i32_r_minMag.c create mode 100755 target-riscv/fpu-custom-riscv/f32_to_i64.c create mode 100755 target-riscv/fpu-custom-riscv/f32_to_i64_r_minMag.c create mode 100755 target-riscv/fpu-custom-riscv/f32_to_ui32.c create mode 100755 target-riscv/fpu-custom-riscv/f32_to_ui32_r_minMag.c create mode 100755 target-riscv/fpu-custom-riscv/f32_to_ui64.c create mode 100755 target-riscv/fpu-custom-riscv/f32_to_ui64_r_minMag.c create mode 100755 target-riscv/fpu-custom-riscv/f64_add.c create mode 100755 target-riscv/fpu-custom-riscv/f64_classify.c create mode 100755 target-riscv/fpu-custom-riscv/f64_div.c create mode 100755 target-riscv/fpu-custom-riscv/f64_eq.c create mode 100755 target-riscv/fpu-custom-riscv/f64_eq_signaling.c create mode 100755 target-riscv/fpu-custom-riscv/f64_isSignalingNaN.c create mode 100755 target-riscv/fpu-custom-riscv/f64_le.c create mode 100755 target-riscv/fpu-custom-riscv/f64_le_quiet.c create mode 100755 target-riscv/fpu-custom-riscv/f64_lt.c create mode 100755 target-riscv/fpu-custom-riscv/f64_lt_quiet.c create mode 100755 target-riscv/fpu-custom-riscv/f64_mul.c create mode 100755 target-riscv/fpu-custom-riscv/f64_mulAdd.c create mode 100755 target-riscv/fpu-custom-riscv/f64_rem.c create mode 100755 target-riscv/fpu-custom-riscv/f64_roundToInt.c create mode 100755 target-riscv/fpu-custom-riscv/f64_sqrt.c create mode 100755 target-riscv/fpu-custom-riscv/f64_sub.c create mode 100755 target-riscv/fpu-custom-riscv/f64_to_f32.c create mode 100755 target-riscv/fpu-custom-riscv/f64_to_i32.c create mode 100755 target-riscv/fpu-custom-riscv/f64_to_i32_r_minMag.c create mode 100755 target-riscv/fpu-custom-riscv/f64_to_i64.c create mode 100755 target-riscv/fpu-custom-riscv/f64_to_i64_r_minMag.c create mode 100755 target-riscv/fpu-custom-riscv/f64_to_ui32.c create mode 100755 target-riscv/fpu-custom-riscv/f64_to_ui32_r_minMag.c create mode 100755 target-riscv/fpu-custom-riscv/f64_to_ui64.c create mode 100755 target-riscv/fpu-custom-riscv/f64_to_ui64_r_minMag.c create mode 100755 target-riscv/fpu-custom-riscv/i32_to_f32.c create mode 100755 target-riscv/fpu-custom-riscv/i32_to_f64.c create mode 100755 target-riscv/fpu-custom-riscv/i64_to_f32.c create mode 100755 target-riscv/fpu-custom-riscv/i64_to_f64.c create mode 100755 target-riscv/fpu-custom-riscv/internals.h create mode 100755 target-riscv/fpu-custom-riscv/platform.h create mode 100755 target-riscv/fpu-custom-riscv/primitives.h create mode 100755 target-riscv/fpu-custom-riscv/s_add128.c create mode 100755 target-riscv/fpu-custom-riscv/s_add192.c create mode 100755 target-riscv/fpu-custom-riscv/s_addMagsF32.c create mode 100755 target-riscv/fpu-custom-riscv/s_addMagsF64.c create mode 100755 target-riscv/fpu-custom-riscv/s_commonNaNToF32UI.c create mode 100755 target-riscv/fpu-custom-riscv/s_commonNaNToF64UI.c create mode 100755 target-riscv/fpu-custom-riscv/s_countLeadingZeros32.c create mode 100755 target-riscv/fpu-custom-riscv/s_countLeadingZeros64.c create mode 100755 target-riscv/fpu-custom-riscv/s_countLeadingZeros8.c create mode 100755 target-riscv/fpu-custom-riscv/s_eq128.c create mode 100755 target-riscv/fpu-custom-riscv/s_estimateDiv128To64.c create mode 100755 target-riscv/fpu-custom-riscv/s_estimateSqrt32.c create mode 100755 target-riscv/fpu-custom-riscv/s_f32UIToCommonNaN.c create mode 100755 target-riscv/fpu-custom-riscv/s_f64UIToCommonNaN.c create mode 100755 target-riscv/fpu-custom-riscv/s_isSigNaNF32UI.c create mode 100755 target-riscv/fpu-custom-riscv/s_isSigNaNF64UI.c create mode 100755 target-riscv/fpu-custom-riscv/s_le128.c create mode 100755 target-riscv/fpu-custom-riscv/s_lt128.c create mode 100755 target-riscv/fpu-custom-riscv/s_mul128By64To192.c create mode 100755 target-riscv/fpu-custom-riscv/s_mul128To256.c create mode 100755 target-riscv/fpu-custom-riscv/s_mul64To128.c create mode 100755 target-riscv/fpu-custom-riscv/s_mulAddF32.c create mode 100755 target-riscv/fpu-custom-riscv/s_mulAddF64.c create mode 100755 target-riscv/fpu-custom-riscv/s_normRoundPackToF32.c create mode 100755 target-riscv/fpu-custom-riscv/s_normRoundPackToF64.c create mode 100755 target-riscv/fpu-custom-riscv/s_normSubnormalF32Sig.c create mode 100755 target-riscv/fpu-custom-riscv/s_normSubnormalF64Sig.c create mode 100755 target-riscv/fpu-custom-riscv/s_propagateNaNF32UI.c create mode 100755 target-riscv/fpu-custom-riscv/s_propagateNaNF64UI.c create mode 100755 target-riscv/fpu-custom-riscv/s_roundPackToF32.c create mode 100755 target-riscv/fpu-custom-riscv/s_roundPackToF64.c create mode 100755 target-riscv/fpu-custom-riscv/s_roundPackToI32.c create mode 100755 target-riscv/fpu-custom-riscv/s_roundPackToI64.c create mode 100755 target-riscv/fpu-custom-riscv/s_roundPackToUI32.c create mode 100755 target-riscv/fpu-custom-riscv/s_roundPackToUI64.c create mode 100755 target-riscv/fpu-custom-riscv/s_shift128ExtraRightJam.c create mode 100755 target-riscv/fpu-custom-riscv/s_shift128RightJam.c create mode 100755 target-riscv/fpu-custom-riscv/s_shift32RightJam.c create mode 100755 target-riscv/fpu-custom-riscv/s_shift64ExtraRightJam.c create mode 100755 target-riscv/fpu-custom-riscv/s_shift64RightJam.c create mode 100755 target-riscv/fpu-custom-riscv/s_shortShift128ExtraRightJam.c create mode 100755 target-riscv/fpu-custom-riscv/s_shortShift128Left.c create mode 100755 target-riscv/fpu-custom-riscv/s_shortShift128Right.c create mode 100755 target-riscv/fpu-custom-riscv/s_shortShift192Left.c create mode 100755 target-riscv/fpu-custom-riscv/s_shortShift32Right1Jam.c create mode 100755 target-riscv/fpu-custom-riscv/s_shortShift64ExtraRightJam.c create mode 100755 target-riscv/fpu-custom-riscv/s_shortShift64RightJam.c create mode 100755 target-riscv/fpu-custom-riscv/s_sub128.c create mode 100755 target-riscv/fpu-custom-riscv/s_sub192.c create mode 100755 target-riscv/fpu-custom-riscv/s_subMagsF32.c create mode 100755 target-riscv/fpu-custom-riscv/s_subMagsF64.c create mode 100644 target-riscv/fpu-custom-riscv/softfloat.ac create mode 100755 target-riscv/fpu-custom-riscv/softfloat.h create mode 100644 target-riscv/fpu-custom-riscv/softfloat.mk.in create mode 100755 target-riscv/fpu-custom-riscv/softfloat_raiseFlags.c create mode 100755 target-riscv/fpu-custom-riscv/softfloat_state.c create mode 100755 target-riscv/fpu-custom-riscv/softfloat_types.h create mode 100755 target-riscv/fpu-custom-riscv/specialize.h create mode 100755 target-riscv/fpu-custom-riscv/ui32_to_f32.c create mode 100755 target-riscv/fpu-custom-riscv/ui32_to_f64.c create mode 100755 target-riscv/fpu-custom-riscv/ui64_to_f32.c create mode 100755 target-riscv/fpu-custom-riscv/ui64_to_f64.c create mode 100644 target-riscv/gdbstub.c create mode 100644 target-riscv/helper.c create mode 100644 target-riscv/helper.h create mode 100644 target-riscv/instmap.h create mode 100644 target-riscv/machine.c create mode 100644 target-riscv/op_helper.c create mode 100644 target-riscv/riscv-defs.h create mode 100644 target-riscv/translate.c create mode 100644 target-riscv/translate_init.c -- 2.7.1