From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56813) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aWrJ5-0004sA-Nk for qemu-devel@nongnu.org; Fri, 19 Feb 2016 15:05:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aWrJ3-0007QP-Uu for qemu-devel@nongnu.org; Fri, 19 Feb 2016 15:05:39 -0500 From: "Edgar E. Iglesias" Date: Fri, 19 Feb 2016 21:04:52 +0100 Message-Id: <1455912292-23807-9-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1455912292-23807-1-git-send-email-edgar.iglesias@gmail.com> References: <1455912292-23807-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v2 8/8] target-arm: Use isyn.swstep.ex to hold the is_ldex state List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com, qemu-arm@nongnu.org, alex.bennee@linaro.org, rth@twiddle.net From: "Edgar E. Iglesias" Switch to using isyn.swstep.ex to hold the is_ldex state for SWStep syndrome generation. No functional change. Signed-off-by: Edgar E. Iglesias --- target-arm/translate-a64.c | 6 +++--- target-arm/translate.c | 6 +++--- target-arm/translate.h | 13 ++++++++----- 3 files changed, 14 insertions(+), 11 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 5250c08..ab249d1 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -260,7 +260,7 @@ static void gen_step_complete_exception(DisasContext *s) * of the exception, and our syndrome information is always correct. */ gen_ss_advance(s); - gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), + gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->isyn.swstep.ex), default_exception_el(s)); s->is_jmp = DISAS_EXC; } @@ -1865,7 +1865,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (is_excl) { if (!is_store) { - s->is_ldex = true; + s->isyn.swstep.ex = true; gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair); } else { gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair); @@ -11136,7 +11136,7 @@ void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb) */ dc->ss_active = ARM_TBFLAG_SS_ACTIVE(tb->flags); dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(tb->flags); - dc->is_ldex = false; + dc->isyn.swstep.ex = false; dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el); init_tmp_a64_array(dc); diff --git a/target-arm/translate.c b/target-arm/translate.c index 7d83c94..5aee066 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -250,7 +250,7 @@ static void gen_step_complete_exception(DisasContext *s) * of the exception, and our syndrome information is always correct. */ gen_ss_advance(s); - gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), + gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->isyn.swstep.ex), default_exception_el(s)); s->is_jmp = DISAS_EXC; } @@ -7431,7 +7431,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, { TCGv_i32 tmp = tcg_temp_new_i32(); - s->is_ldex = true; + s->isyn.swstep.ex = true; switch (size) { case 0: @@ -11341,7 +11341,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb) */ dc->ss_active = ARM_TBFLAG_SS_ACTIVE(tb->flags); dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(tb->flags); - dc->is_ldex = false; + dc->isyn.swstep.ex = false; dc->ss_same_el = false; /* Can't be true since EL_d must be AArch64 */ cpu_F0s = tcg_temp_new_i32(); diff --git a/target-arm/translate.h b/target-arm/translate.h index e002c90..1c4c087 100644 --- a/target-arm/translate.h +++ b/target-arm/translate.h @@ -49,11 +49,6 @@ typedef struct DisasContext { */ bool ss_active; bool pstate_ss; - /* True if the insn just emitted was a load-exclusive instruction - * (necessary for syndrome information for single step exceptions), - * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*. - */ - bool is_ldex; /* True if a single-step exception will be taken to the current EL */ bool ss_same_el; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ @@ -69,6 +64,14 @@ typedef struct DisasContext { bool sf; bool ar; } dabt; + /* SWStep section. */ + struct { + /* True if the insn just emitted was a load-exclusive instruction + * (necessary for syndrome information for single step exceptions), + * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*. + */ + bool ex; + } swstep; } isyn; /* TCG op index of the current insn_start. */ int insn_start_idx; -- 1.9.1