From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50852) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aYKFz-0005uO-E9 for qemu-devel@nongnu.org; Tue, 23 Feb 2016 16:12:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aYKFu-0001Ia-H7 for qemu-devel@nongnu.org; Tue, 23 Feb 2016 16:12:31 -0500 Received: from mail-qg0-x230.google.com ([2607:f8b0:400d:c04::230]:33426) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aYKFu-0001IS-Bc for qemu-devel@nongnu.org; Tue, 23 Feb 2016 16:12:26 -0500 Received: by mail-qg0-x230.google.com with SMTP id b35so146954968qge.0 for ; Tue, 23 Feb 2016 13:12:26 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Tue, 23 Feb 2016 13:11:44 -0800 Message-Id: <1456261920-29900-9-git-send-email-rth@twiddle.net> In-Reply-To: <1456261920-29900-1-git-send-email-rth@twiddle.net> References: <1456261920-29900-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v2 08/24] target-sparc: Pass TCGMemOp to gen_ld/st_asi List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Signed-off-by: Richard Henderson --- target-sparc/translate.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index c9ec885..c1cb1e1 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -2004,7 +2004,7 @@ static DisasASI get_asi(DisasContext *dc, int insn) } static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, - int insn, int size, int sign) + int insn, TCGMemOp memop) { DisasASI da = get_asi(dc, insn); @@ -2014,8 +2014,8 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, default: { TCGv_i32 r_asi = tcg_const_i32(da.asi); - TCGv_i32 r_size = tcg_const_i32(size); - TCGv_i32 r_sign = tcg_const_i32(sign); + TCGv_i32 r_size = tcg_const_i32(1 << (memop & MO_SIZE)); + TCGv_i32 r_sign = tcg_const_i32(!!(memop & MO_SIGN)); save_state(dc); #ifdef TARGET_SPARC64 @@ -2037,7 +2037,7 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, } static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, - int insn, int size) + int insn, TCGMemOp memop) { DisasASI da = get_asi(dc, insn); @@ -2047,7 +2047,7 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, default: { TCGv_i32 r_asi = tcg_const_i32(da.asi); - TCGv_i32 r_size = tcg_const_i32(size); + TCGv_i32 r_size = tcg_const_i32(1 << (memop & MO_SIZE)); save_state(dc); #ifdef TARGET_SPARC64 @@ -4815,13 +4815,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) case 0x10: /* lda, V9 lduwa, load word alternate */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, 4, 0); + gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL); break; case 0x11: /* lduba, load unsigned byte alternate */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, 1, 0); + gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_UB); break; case 0x12: /* lduha, load unsigned halfword alternate */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, 2, 0); + gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW); break; case 0x13: /* ldda, load double word alternate */ if (rd & 1) { @@ -4830,10 +4830,10 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) gen_ldda_asi(dc, cpu_val, cpu_addr, insn, rd); goto skip_move; case 0x19: /* ldsba, load signed byte alternate */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, 1, 1); + gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_SB); break; case 0x1a: /* ldsha, load signed halfword alternate */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, 2, 1); + gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESW); break; case 0x1d: /* ldstuba -- XXX: should be atomically */ gen_ldstub_asi(dc, cpu_val, cpu_addr, insn); @@ -4862,10 +4862,10 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx); break; case 0x18: /* V9 ldswa */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, 4, 1); + gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL); break; case 0x1b: /* V9 ldxa */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, 8, 0); + gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEQ); break; case 0x2d: /* V9 prefetch, no effect */ goto skip_move; @@ -4997,13 +4997,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) case 0x14: /* sta, V9 stwa, store word alternate */ - gen_st_asi(dc, cpu_val, cpu_addr, insn, 4); + gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL); break; case 0x15: /* stba, store byte alternate */ - gen_st_asi(dc, cpu_val, cpu_addr, insn, 1); + gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_UB); break; case 0x16: /* stha, store halfword alternate */ - gen_st_asi(dc, cpu_val, cpu_addr, insn, 2); + gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW); break; case 0x17: /* stda, store double word alternate */ if (rd & 1) { @@ -5018,7 +5018,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx); break; case 0x1e: /* V9 stxa */ - gen_st_asi(dc, cpu_val, cpu_addr, insn, 8); + gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEQ); break; #endif default: -- 2.5.0