* [Qemu-devel] [PATCH 1/3] target-ppc: Use movcond in isel
2016-02-24 1:18 [Qemu-devel] [PATCH 0/3] target-ppc improvements Richard Henderson
@ 2016-02-24 1:18 ` Richard Henderson
2016-02-24 1:18 ` [Qemu-devel] [PATCH 2/3] target-ppc: Use 32-bit rotate instead of deposit + 64-bit rotate Richard Henderson
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Richard Henderson @ 2016-02-24 1:18 UTC (permalink / raw)
To: qemu-devel; +Cc: agraf
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-ppc/translate.c | 29 +++++++++++------------------
1 file changed, 11 insertions(+), 18 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index ecc85f0..00c9a5a 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -755,27 +755,20 @@ static void gen_cmpli(DisasContext *ctx)
/* isel (PowerPC 2.03 specification) */
static void gen_isel(DisasContext *ctx)
{
- TCGLabel *l1, *l2;
uint32_t bi = rC(ctx->opcode);
- uint32_t mask;
- TCGv_i32 t0;
+ uint32_t mask = 0x08 >> (bi & 0x03);
+ TCGv t0 = tcg_temp_new();
+ TCGv zr;
- l1 = gen_new_label();
- l2 = gen_new_label();
+ tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
+ tcg_gen_andi_tl(t0, t0, mask);
- mask = 0x08 >> (bi & 0x03);
- t0 = tcg_temp_new_i32();
- tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
- tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
- if (rA(ctx->opcode) == 0)
- tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
- else
- tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
- tcg_gen_br(l2);
- gen_set_label(l1);
- tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
- gen_set_label(l2);
- tcg_temp_free_i32(t0);
+ zr = tcg_const_tl(0);
+ tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
+ rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
+ cpu_gpr[rB(ctx->opcode)]);
+ tcg_temp_free(zr);
+ tcg_temp_free(t0);
}
/* cmpb: PowerPC 2.05 specification */
--
2.5.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* [Qemu-devel] [PATCH 2/3] target-ppc: Use 32-bit rotate instead of deposit + 64-bit rotate
2016-02-24 1:18 [Qemu-devel] [PATCH 0/3] target-ppc improvements Richard Henderson
2016-02-24 1:18 ` [Qemu-devel] [PATCH 1/3] target-ppc: Use movcond in isel Richard Henderson
@ 2016-02-24 1:18 ` Richard Henderson
2016-02-24 1:18 ` [Qemu-devel] [PATCH 3/3] target-ppc: Cleanups to rldinm, rldnm, rldimi Richard Henderson
2016-03-15 23:57 ` [Qemu-devel] [PATCH 0/3] target-ppc improvements David Gibson
3 siblings, 0 replies; 5+ messages in thread
From: Richard Henderson @ 2016-02-24 1:18 UTC (permalink / raw)
To: qemu-devel; +Cc: agraf
A 32-bit rotate insn is more common on hosts than a deposit insn,
and if the host has neither the result is truely horrific.
At the same time, tidy up the temporaries within these functions,
drop the over-use of "likely", drop some checks for identity that
will also be checked by tcg-op.c functions, and special case mask
without rotate within rlwinm.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-ppc/translate.c | 172 ++++++++++++++++++++-----------------------------
1 file changed, 70 insertions(+), 102 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 00c9a5a..b575609 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1609,141 +1609,109 @@ static void gen_cntlzd(DisasContext *ctx)
/* rlwimi & rlwimi. */
static void gen_rlwimi(DisasContext *ctx)
{
- uint32_t mb, me, sh;
-
- mb = MB(ctx->opcode);
- me = ME(ctx->opcode);
- sh = SH(ctx->opcode);
- if (likely(sh == (31-me) && mb <= me)) {
- tcg_gen_deposit_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
- cpu_gpr[rS(ctx->opcode)], sh, me - mb + 1);
+ TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
+ TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
+ uint32_t sh = SH(ctx->opcode);
+ uint32_t mb = MB(ctx->opcode);
+ uint32_t me = ME(ctx->opcode);
+
+ if (sh == (31-me) && mb <= me) {
+ tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
} else {
target_ulong mask;
+ TCGv_i32 t0;
TCGv t1;
- TCGv t0 = tcg_temp_new();
-#if defined(TARGET_PPC64)
- tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
- cpu_gpr[rS(ctx->opcode)], 32, 32);
- tcg_gen_rotli_i64(t0, t0, sh);
-#else
- tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
-#endif
+
#if defined(TARGET_PPC64)
mb += 32;
me += 32;
#endif
mask = MASK(mb, me);
+
+ t0 = tcg_temp_new_i32();
t1 = tcg_temp_new();
- tcg_gen_andi_tl(t0, t0, mask);
- tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
- tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
- tcg_temp_free(t0);
+ tcg_gen_trunc_tl_i32(t0, t_rs);
+ tcg_gen_rotli_i32(t0, t0, sh);
+ tcg_gen_extu_i32_tl(t1, t0);
+ tcg_temp_free_i32(t0);
+
+ tcg_gen_andi_tl(t1, t1, mask);
+ tcg_gen_andi_tl(t_ra, t_ra, ~mask);
+ tcg_gen_or_tl(t_ra, t_ra, t1);
tcg_temp_free(t1);
}
- if (unlikely(Rc(ctx->opcode) != 0))
- gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
+ if (unlikely(Rc(ctx->opcode) != 0)) {
+ gen_set_Rc0(ctx, t_ra);
+ }
}
/* rlwinm & rlwinm. */
static void gen_rlwinm(DisasContext *ctx)
{
- uint32_t mb, me, sh;
-
- sh = SH(ctx->opcode);
- mb = MB(ctx->opcode);
- me = ME(ctx->opcode);
+ TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
+ TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
+ uint32_t sh = SH(ctx->opcode);
+ uint32_t mb = MB(ctx->opcode);
+ uint32_t me = ME(ctx->opcode);
- if (likely(mb == 0 && me == (31 - sh))) {
- if (likely(sh == 0)) {
- tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
- } else {
- TCGv t0 = tcg_temp_new();
- tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
- tcg_gen_shli_tl(t0, t0, sh);
- tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
- tcg_temp_free(t0);
- }
- } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
- TCGv t0 = tcg_temp_new();
- tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
- tcg_gen_shri_tl(t0, t0, mb);
- tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
- tcg_temp_free(t0);
- } else if (likely(mb == 0 && me == 31)) {
- TCGv_i32 t0 = tcg_temp_new_i32();
- tcg_gen_trunc_tl_i32(t0, cpu_gpr[rS(ctx->opcode)]);
- tcg_gen_rotli_i32(t0, t0, sh);
- tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t0);
- tcg_temp_free_i32(t0);
+ if (mb == 0 && me == (31 - sh)) {
+ tcg_gen_shli_tl(t_ra, t_rs, sh);
+ tcg_gen_ext32u_tl(t_ra, t_ra);
+ } else if (sh != 0 && me == 31 && sh == (32 - mb)) {
+ tcg_gen_ext32u_tl(t_ra, t_rs);
+ tcg_gen_shri_tl(t_ra, t_ra, mb);
} else {
- TCGv t0 = tcg_temp_new();
-#if defined(TARGET_PPC64)
- tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
- cpu_gpr[rS(ctx->opcode)], 32, 32);
- tcg_gen_rotli_i64(t0, t0, sh);
-#else
- tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
-#endif
#if defined(TARGET_PPC64)
mb += 32;
me += 32;
#endif
- tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
- tcg_temp_free(t0);
+ if (sh == 0) {
+ tcg_gen_andi_tl(t_ra, t_rs, MASK(mb, me));
+ } else {
+ TCGv_i32 t0 = tcg_temp_new_i32();
+
+ tcg_gen_trunc_tl_i32(t0, t_rs);
+ tcg_gen_rotli_i32(t0, t0, sh);
+ tcg_gen_andi_i32(t0, t0, MASK(mb, me));
+ tcg_gen_extu_i32_tl(t_ra, t0);
+ tcg_temp_free_i32(t0);
+ }
+ }
+ if (unlikely(Rc(ctx->opcode) != 0)) {
+ gen_set_Rc0(ctx, t_ra);
}
- if (unlikely(Rc(ctx->opcode) != 0))
- gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
/* rlwnm & rlwnm. */
static void gen_rlwnm(DisasContext *ctx)
{
- uint32_t mb, me;
- mb = MB(ctx->opcode);
- me = ME(ctx->opcode);
+ TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
+ TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
+ TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
+ uint32_t mb = MB(ctx->opcode);
+ uint32_t me = ME(ctx->opcode);
+ TCGv_i32 t0, t1;
- if (likely(mb == 0 && me == 31)) {
- TCGv_i32 t0, t1;
- t0 = tcg_temp_new_i32();
- t1 = tcg_temp_new_i32();
- tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]);
- tcg_gen_trunc_tl_i32(t1, cpu_gpr[rS(ctx->opcode)]);
- tcg_gen_andi_i32(t0, t0, 0x1f);
- tcg_gen_rotl_i32(t1, t1, t0);
- tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t1);
- tcg_temp_free_i32(t0);
- tcg_temp_free_i32(t1);
- } else {
- TCGv t0;
#if defined(TARGET_PPC64)
- TCGv t1;
+ mb += 32;
+ me += 32;
#endif
- t0 = tcg_temp_new();
- tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
-#if defined(TARGET_PPC64)
- t1 = tcg_temp_new_i64();
- tcg_gen_deposit_i64(t1, cpu_gpr[rS(ctx->opcode)],
- cpu_gpr[rS(ctx->opcode)], 32, 32);
- tcg_gen_rotl_i64(t0, t1, t0);
- tcg_temp_free_i64(t1);
-#else
- tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
-#endif
- if (unlikely(mb != 0 || me != 31)) {
-#if defined(TARGET_PPC64)
- mb += 32;
- me += 32;
-#endif
- tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
- } else {
- tcg_gen_andi_tl(t0, t0, MASK(32, 63));
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
- }
- tcg_temp_free(t0);
+ t0 = tcg_temp_new_i32();
+ t1 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(t0, t_rb);
+ tcg_gen_trunc_tl_i32(t1, t_rs);
+ tcg_gen_andi_i32(t0, t0, 0x1f);
+ tcg_gen_rotl_i32(t1, t1, t0);
+ tcg_temp_free_i32(t0);
+
+ tcg_gen_andi_i32(t1, t1, MASK(mb, me));
+ tcg_gen_extu_i32_tl(t_ra, t1);
+ tcg_temp_free_i32(t1);
+
+ if (unlikely(Rc(ctx->opcode) != 0)) {
+ gen_set_Rc0(ctx, t_ra);
}
- if (unlikely(Rc(ctx->opcode) != 0))
- gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
#if defined(TARGET_PPC64)
--
2.5.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* [Qemu-devel] [PATCH 3/3] target-ppc: Cleanups to rldinm, rldnm, rldimi
2016-02-24 1:18 [Qemu-devel] [PATCH 0/3] target-ppc improvements Richard Henderson
2016-02-24 1:18 ` [Qemu-devel] [PATCH 1/3] target-ppc: Use movcond in isel Richard Henderson
2016-02-24 1:18 ` [Qemu-devel] [PATCH 2/3] target-ppc: Use 32-bit rotate instead of deposit + 64-bit rotate Richard Henderson
@ 2016-02-24 1:18 ` Richard Henderson
2016-03-15 23:57 ` [Qemu-devel] [PATCH 0/3] target-ppc improvements David Gibson
3 siblings, 0 replies; 5+ messages in thread
From: Richard Henderson @ 2016-02-24 1:18 UTC (permalink / raw)
To: qemu-devel; +Cc: agraf
Mirror the cleanups just done to rlwinm, rlwnm and rlwimi.
This adds use of deposit to rldimi.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-ppc/translate.c | 91 +++++++++++++++++++++++++-------------------------
1 file changed, 46 insertions(+), 45 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index b575609..72c1648 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1746,26 +1746,24 @@ static void glue(gen_, name##3)(DisasContext *ctx) \
gen_##name(ctx, 1, 1); \
}
-static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
- uint32_t sh)
+static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
{
- if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
- tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
- } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
- tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
+ TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
+ TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
+
+ if (sh != 0 && mb == 0 && me == (63 - sh)) {
+ tcg_gen_shli_tl(t_ra, t_rs, sh);
+ } else if (sh != 0 && me == 63 && sh == (64 - mb)) {
+ tcg_gen_shri_tl(t_ra, t_rs, mb);
} else {
- TCGv t0 = tcg_temp_new();
- tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
- if (likely(mb == 0 && me == 63)) {
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
- } else {
- tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
- }
- tcg_temp_free(t0);
+ tcg_gen_rotli_tl(t_ra, t_rs, sh);
+ tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
+ }
+ if (unlikely(Rc(ctx->opcode) != 0)) {
+ gen_set_Rc0(ctx, t_ra);
}
- if (unlikely(Rc(ctx->opcode) != 0))
- gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
+
/* rldicl - rldicl. */
static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
{
@@ -1776,6 +1774,7 @@ static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
gen_rldinm(ctx, mb, 63, sh);
}
GEN_PPC64_R4(rldicl, 0x1E, 0x00);
+
/* rldicr - rldicr. */
static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
{
@@ -1786,6 +1785,7 @@ static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
gen_rldinm(ctx, 0, me, sh);
}
GEN_PPC64_R4(rldicr, 0x1E, 0x02);
+
/* rldic - rldic. */
static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
{
@@ -1797,21 +1797,22 @@ static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
}
GEN_PPC64_R4(rldic, 0x1E, 0x04);
-static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
+static void gen_rldnm(DisasContext *ctx, int mb, int me)
{
+ TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
+ TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
+ TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
TCGv t0;
t0 = tcg_temp_new();
- tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
- tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
- if (unlikely(mb != 0 || me != 63)) {
- tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
- } else {
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
- }
+ tcg_gen_andi_tl(t0, t_rb, 0x3f);
+ tcg_gen_rotl_tl(t_ra, t_rs, t0);
tcg_temp_free(t0);
- if (unlikely(Rc(ctx->opcode) != 0))
- gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
+
+ tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
+ if (unlikely(Rc(ctx->opcode) != 0)) {
+ gen_set_Rc0(ctx, t_ra);
+ }
}
/* rldcl - rldcl. */
@@ -1823,6 +1824,7 @@ static inline void gen_rldcl(DisasContext *ctx, int mbn)
gen_rldnm(ctx, mb, 63);
}
GEN_PPC64_R2(rldcl, 0x1E, 0x08);
+
/* rldcr - rldcr. */
static inline void gen_rldcr(DisasContext *ctx, int men)
{
@@ -1832,32 +1834,31 @@ static inline void gen_rldcr(DisasContext *ctx, int men)
gen_rldnm(ctx, 0, me);
}
GEN_PPC64_R2(rldcr, 0x1E, 0x09);
+
/* rldimi - rldimi. */
-static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
+static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
{
- uint32_t sh, mb, me;
+ TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
+ TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
+ uint32_t sh = SH(ctx->opcode) | (shn << 5);
+ uint32_t mb = MB(ctx->opcode) | (mbn << 5);
+ uint32_t me = 63 - sh;
- sh = SH(ctx->opcode) | (shn << 5);
- mb = MB(ctx->opcode) | (mbn << 5);
- me = 63 - sh;
- if (unlikely(sh == 0 && mb == 0)) {
- tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
+ if (mb <= me) {
+ tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
} else {
- TCGv t0, t1;
- target_ulong mask;
+ target_ulong mask = MASK(mb, me);
+ TCGv t1 = tcg_temp_new();
- t0 = tcg_temp_new();
- tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
- t1 = tcg_temp_new();
- mask = MASK(mb, me);
- tcg_gen_andi_tl(t0, t0, mask);
- tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
- tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
- tcg_temp_free(t0);
+ tcg_gen_rotli_tl(t1, t_rs, sh);
+ tcg_gen_andi_tl(t1, t1, mask);
+ tcg_gen_andi_tl(t_ra, t_ra, ~mask);
+ tcg_gen_or_tl(t_ra, t_ra, t1);
tcg_temp_free(t1);
}
- if (unlikely(Rc(ctx->opcode) != 0))
- gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
+ if (unlikely(Rc(ctx->opcode) != 0)) {
+ gen_set_Rc0(ctx, t_ra);
+ }
}
GEN_PPC64_R4(rldimi, 0x1E, 0x06);
#endif
--
2.5.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [Qemu-devel] [PATCH 0/3] target-ppc improvements
2016-02-24 1:18 [Qemu-devel] [PATCH 0/3] target-ppc improvements Richard Henderson
` (2 preceding siblings ...)
2016-02-24 1:18 ` [Qemu-devel] [PATCH 3/3] target-ppc: Cleanups to rldinm, rldnm, rldimi Richard Henderson
@ 2016-03-15 23:57 ` David Gibson
3 siblings, 0 replies; 5+ messages in thread
From: David Gibson @ 2016-03-15 23:57 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, agraf
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On Tue, Feb 23, 2016 at 05:18:33PM -0800, Richard Henderson wrote:
> The ISEL patch was posted last year; I don't believe I ever
> got around to posting these other two.
I'm not entirely clear if these are just cleanups / optimizations, or
if they also fix actual bugs.
If the former, I'm inclined to leave these until the 2.7 cycle. So,
for the time being I've applied these to a new ppc-for-2.7 branch.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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