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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 09/20] target-arm: In v8, make illegal AArch32 mode changes set PSTATE.IL
Date: Fri, 26 Feb 2016 15:20:14 +0000	[thread overview]
Message-ID: <1456500025-28761-10-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1456500025-28761-1-git-send-email-peter.maydell@linaro.org>

In v8, the illegal mode changes which are UNPREDICTABLE in v7 are
given architected behaviour:
 * the mode field is unchanged
 * PSTATE.IL is set (so any subsequent instructions will UNDEF)
 * any other CPSR fields are written to as normal

This is pretty much the same behaviour we picked for our
UNPREDICTABLE handling, with the exception that for v8 we
need to set the IL bit.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1455556977-3644-10-git-send-email-peter.maydell@linaro.org
---
 target-arm/helper.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 5926b15..ff5f895 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5325,11 +5325,20 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
         (env->uncached_cpsr & CPSR_M) != CPSR_USER &&
         ((env->uncached_cpsr ^ val) & mask & CPSR_M)) {
         if (bad_mode_switch(env, val & CPSR_M)) {
-            /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
-             * We choose to ignore the attempt and leave the CPSR M field
-             * untouched.
+            /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
+             * v7, and has defined behaviour in v8:
+             *  + leave CPSR.M untouched
+             *  + allow changes to the other CPSR fields
+             *  + set PSTATE.IL
+             * For user changes via the GDB stub, we don't set PSTATE.IL,
+             * as this would be unnecessarily harsh for a user error.
              */
             mask &= ~CPSR_M;
+            if (write_type != CPSRWriteByGDBStub &&
+                arm_feature(env, ARM_FEATURE_V8)) {
+                mask |= CPSR_IL;
+                val |= CPSR_IL;
+            }
         } else {
             switch_mode(env, val & CPSR_M);
         }
-- 
1.9.1

  parent reply	other threads:[~2016-02-26 15:20 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-02-26 15:20 [Qemu-devel] [PULL 00/20] target-arm queue Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 01/20] target-arm: Give CPSR setting on 32-bit exception return its own helper Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 02/20] target-arm: Add write_type argument to cpsr_write() Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 03/20] target-arm: Raw CPSR writes should skip checks and bank switching Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 04/20] linux-user: Use restrictive mask when calling cpsr_write() Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 05/20] target-arm: In cpsr_write() ignore mode switches from User mode Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 06/20] target-arm: Add comment about not implementing NSACR.RFR Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 07/20] target-arm: Add Hyp mode checks to bad_mode_switch() Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 08/20] target-arm: Forbid mode switch to Mon from Secure EL1 Peter Maydell
2016-02-26 15:20 ` Peter Maydell [this message]
2016-02-26 15:20 ` [Qemu-devel] [PULL 10/20] target-arm: Make mode switches from Hyp via CPS and MRS illegal Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 11/20] target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1 Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 12/20] target-arm: Fix handling of SDCR for 32-bit code Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 13/20] target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 14/20] ARM: PL061: Checking register r/w accesses to reserved area Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 15/20] raspi: fix SD card with recent sdhci changes Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 16/20] MAINTAINERS: Add some missing ARM related header files Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 17/20] sdhci: Revert "add optional quirk property to disable card insertion/removal interrupts" Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 18/20] sdhci: add quirk property for card insert interrupt status on Raspberry Pi Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 19/20] target-arm: Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 20/20] target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF Peter Maydell
2016-02-26 16:42 ` [Qemu-devel] [PULL 00/20] target-arm queue Peter Maydell

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