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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 11/20] target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1
Date: Fri, 26 Feb 2016 15:20:16 +0000	[thread overview]
Message-ID: <1456500025-28761-12-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1456500025-28761-1-git-send-email-peter.maydell@linaro.org>

If HCR.TGE is 1 then mode changes via CPS and MSR from Monitor to
NonSecure PL1 modes are illegal mode changes. Implement this check
in bad_mode_switch().

(We don't currently implement HCR.TGE, but this is the only missing
check from the v8 ARM ARM G1.9.3 and so it's worth adding now; the
rest of the HCR.TGE checks can be added later as necessary.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1455556977-3644-12-git-send-email-peter.maydell@linaro.org
---
 target-arm/helper.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 24ea48e..3d7fda1 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5216,6 +5216,7 @@ static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
 
     switch (mode) {
     case ARM_CPU_MODE_USR:
+        return 0;
     case ARM_CPU_MODE_SYS:
     case ARM_CPU_MODE_SVC:
     case ARM_CPU_MODE_ABT:
@@ -5225,6 +5226,15 @@ static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
         /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
          * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
          */
+        /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
+         * and CPS are treated as illegal mode changes.
+         */
+        if (write_type == CPSRWriteByInstr &&
+            (env->cp15.hcr_el2 & HCR_TGE) &&
+            (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON &&
+            !arm_is_secure_below_el3(env)) {
+            return 1;
+        }
         return 0;
     case ARM_CPU_MODE_HYP:
         return !arm_feature(env, ARM_FEATURE_EL2)
-- 
1.9.1

  parent reply	other threads:[~2016-02-26 15:20 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-02-26 15:20 [Qemu-devel] [PULL 00/20] target-arm queue Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 01/20] target-arm: Give CPSR setting on 32-bit exception return its own helper Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 02/20] target-arm: Add write_type argument to cpsr_write() Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 03/20] target-arm: Raw CPSR writes should skip checks and bank switching Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 04/20] linux-user: Use restrictive mask when calling cpsr_write() Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 05/20] target-arm: In cpsr_write() ignore mode switches from User mode Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 06/20] target-arm: Add comment about not implementing NSACR.RFR Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 07/20] target-arm: Add Hyp mode checks to bad_mode_switch() Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 08/20] target-arm: Forbid mode switch to Mon from Secure EL1 Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 09/20] target-arm: In v8, make illegal AArch32 mode changes set PSTATE.IL Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 10/20] target-arm: Make mode switches from Hyp via CPS and MRS illegal Peter Maydell
2016-02-26 15:20 ` Peter Maydell [this message]
2016-02-26 15:20 ` [Qemu-devel] [PULL 12/20] target-arm: Fix handling of SDCR for 32-bit code Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 13/20] target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 14/20] ARM: PL061: Checking register r/w accesses to reserved area Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 15/20] raspi: fix SD card with recent sdhci changes Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 16/20] MAINTAINERS: Add some missing ARM related header files Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 17/20] sdhci: Revert "add optional quirk property to disable card insertion/removal interrupts" Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 18/20] sdhci: add quirk property for card insert interrupt status on Raspberry Pi Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 19/20] target-arm: Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW Peter Maydell
2016-02-26 15:20 ` [Qemu-devel] [PULL 20/20] target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF Peter Maydell
2016-02-26 16:42 ` [Qemu-devel] [PULL 00/20] target-arm queue Peter Maydell

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