From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37307) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aZKC2-0007UK-HQ for qemu-devel@nongnu.org; Fri, 26 Feb 2016 10:20:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aZKC1-0004mw-O2 for qemu-devel@nongnu.org; Fri, 26 Feb 2016 10:20:34 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:55998) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aZKC1-0004mY-IB for qemu-devel@nongnu.org; Fri, 26 Feb 2016 10:20:33 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84) (envelope-from ) id 1aZKC1-0003NX-AT for qemu-devel@nongnu.org; Fri, 26 Feb 2016 15:20:33 +0000 From: Peter Maydell Date: Fri, 26 Feb 2016 15:20:16 +0000 Message-Id: <1456500025-28761-12-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1456500025-28761-1-git-send-email-peter.maydell@linaro.org> References: <1456500025-28761-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 11/20] target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org If HCR.TGE is 1 then mode changes via CPS and MSR from Monitor to NonSecure PL1 modes are illegal mode changes. Implement this check in bad_mode_switch(). (We don't currently implement HCR.TGE, but this is the only missing check from the v8 ARM ARM G1.9.3 and so it's worth adding now; the rest of the HCR.TGE checks can be added later as necessary.) Signed-off-by: Peter Maydell Reviewed-by: Sergey Fedorov Message-id: 1455556977-3644-12-git-send-email-peter.maydell@linaro.org --- target-arm/helper.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 24ea48e..3d7fda1 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -5216,6 +5216,7 @@ static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) switch (mode) { case ARM_CPU_MODE_USR: + return 0; case ARM_CPU_MODE_SYS: case ARM_CPU_MODE_SVC: case ARM_CPU_MODE_ABT: @@ -5225,6 +5226,15 @@ static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) */ + /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR + * and CPS are treated as illegal mode changes. + */ + if (write_type == CPSRWriteByInstr && + (env->cp15.hcr_el2 & HCR_TGE) && + (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && + !arm_is_secure_below_el3(env)) { + return 1; + } return 0; case ARM_CPU_MODE_HYP: return !arm_feature(env, ARM_FEATURE_EL2) -- 1.9.1