From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37274) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aZKC1-0007Rv-Al for qemu-devel@nongnu.org; Fri, 26 Feb 2016 10:20:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aZKC0-0004m1-8u for qemu-devel@nongnu.org; Fri, 26 Feb 2016 10:20:33 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:55996) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aZKC0-0004kv-2R for qemu-devel@nongnu.org; Fri, 26 Feb 2016 10:20:32 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84) (envelope-from ) id 1aZKBw-0003JJ-Fp for qemu-devel@nongnu.org; Fri, 26 Feb 2016 15:20:28 +0000 From: Peter Maydell Date: Fri, 26 Feb 2016 15:20:06 +0000 Message-Id: <1456500025-28761-2-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1456500025-28761-1-git-send-email-peter.maydell@linaro.org> References: <1456500025-28761-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 01/20] target-arm: Give CPSR setting on 32-bit exception return its own helper List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org The rules for setting the CPSR on a 32-bit exception return are subtly different from those for setting the CPSR via an instruction like MSR or CPS. (In particular, in Hyp mode changing the mode bits is not valid via MSR or CPS.) Split the exception-return case into its own helper for setting CPSR, so we can eventually handle them differently in the helper function. Signed-off-by: Peter Maydell Reviewed-by: Sergey Fedorov Message-id: 1455556977-3644-2-git-send-email-peter.maydell@linaro.org --- target-arm/helper.h | 1 + target-arm/op_helper.c | 6 ++++++ target-arm/translate.c | 6 +++--- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/target-arm/helper.h b/target-arm/helper.h index c98e9ce..ea13202 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -57,6 +57,7 @@ DEF_HELPER_2(pre_smc, void, env, i32) DEF_HELPER_1(check_breakpoints, void, env) DEF_HELPER_3(cpsr_write, void, env, i32, i32) +DEF_HELPER_2(cpsr_write_eret, void, env, i32) DEF_HELPER_1(cpsr_read, i32, env) DEF_HELPER_3(v7m_msr, void, env, i32, i32) diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 538887c..e3ddd5a 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -425,6 +425,12 @@ void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) cpsr_write(env, val, mask); } +/* Write the CPSR for a 32-bit exception return */ +void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) +{ + cpsr_write(env, val, CPSR_ERET_MASK); +} + /* Access to user mode registers from privileged modes. */ uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno) { diff --git a/target-arm/translate.c b/target-arm/translate.c index e69145d..413f7de 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -4094,7 +4094,7 @@ static void gen_exception_return(DisasContext *s, TCGv_i32 pc) TCGv_i32 tmp; store_reg(s, 15, pc); tmp = load_cpu_field(spsr); - gen_set_cpsr(tmp, CPSR_ERET_MASK); + gen_helper_cpsr_write_eret(cpu_env, tmp); tcg_temp_free_i32(tmp); s->is_jmp = DISAS_JUMP; } @@ -4102,7 +4102,7 @@ static void gen_exception_return(DisasContext *s, TCGv_i32 pc) /* Generate a v6 exception return. Marks both values as dead. */ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCGv_i32 cpsr) { - gen_set_cpsr(cpsr, CPSR_ERET_MASK); + gen_helper_cpsr_write_eret(cpu_env, cpsr); tcg_temp_free_i32(cpsr); store_reg(s, 15, pc); s->is_jmp = DISAS_JUMP; @@ -9094,7 +9094,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) if (exc_return) { /* Restore CPSR from SPSR. */ tmp = load_cpu_field(spsr); - gen_set_cpsr(tmp, CPSR_ERET_MASK); + gen_helper_cpsr_write_eret(cpu_env, tmp); tcg_temp_free_i32(tmp); s->is_jmp = DISAS_JUMP; } -- 1.9.1