From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37242) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aZKC0-0007Pw-DM for qemu-devel@nongnu.org; Fri, 26 Feb 2016 10:20:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aZKBz-0004lH-GA for qemu-devel@nongnu.org; Fri, 26 Feb 2016 10:20:32 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:55996) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aZKBz-0004kv-9n for qemu-devel@nongnu.org; Fri, 26 Feb 2016 10:20:31 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84) (envelope-from ) id 1aZKBy-0003LD-RN for qemu-devel@nongnu.org; Fri, 26 Feb 2016 15:20:30 +0000 From: Peter Maydell Date: Fri, 26 Feb 2016 15:20:11 +0000 Message-Id: <1456500025-28761-7-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1456500025-28761-1-git-send-email-peter.maydell@linaro.org> References: <1456500025-28761-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 06/20] target-arm: Add comment about not implementing NSACR.RFR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org QEMU doesn't implement the NSACR.RFR bit, which is a permitted IMPDEF in choice in ARMv7 and the only permitted choice in ARMv8. Add a comment to bad_mode_switch() to note that this is why FIQ is always a valid mode regardless of the CPU's Secure state. Signed-off-by: Peter Maydell Reviewed-by: Sergey Fedorov Message-id: 1455556977-3644-7-git-send-email-peter.maydell@linaro.org --- target-arm/helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index b2d2440..57cc879 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -5214,6 +5214,9 @@ static int bad_mode_switch(CPUARMState *env, int mode) case ARM_CPU_MODE_UND: case ARM_CPU_MODE_IRQ: case ARM_CPU_MODE_FIQ: + /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 + * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) + */ return 0; case ARM_CPU_MODE_MON: return !arm_is_secure(env); -- 1.9.1