From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36545) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aakzZ-0004Av-6g for qemu-devel@nongnu.org; Tue, 01 Mar 2016 09:09:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aakzV-0004mI-0C for qemu-devel@nongnu.org; Tue, 01 Mar 2016 09:09:37 -0500 Received: from mx1.redhat.com ([209.132.183.28]:51410) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aakzU-0004m7-QV for qemu-devel@nongnu.org; Tue, 01 Mar 2016 09:09:32 -0500 From: Paolo Bonzini Date: Tue, 1 Mar 2016 15:09:30 +0100 Message-Id: <1456841370-14602-1-git-send-email-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH] target-i386: fix interrupt shadow List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: hpoussin@reactos.org The handling of the interrupt shadow is subtle. QEMU's check to stop the interrupt shadow needs to check the state after the _penultimate_ instruction. Because the interrupt shadow is only enabled at the end of a translation block, and it makes the next, the state at the penultimate instruction is stored in the current translation block's flags. Fix gen_eob to check it correctly. This fixes Windows XP. Reported-by: Herv=C3=A9 Poussineau Fixes: 7f0b7141b4c7deab51efd8ee1e83eab2d9b7a9ea Signed-off-by: Paolo Bonzini --- target-i386/translate.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 9171929..0ed2ee9 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -2424,7 +2424,14 @@ static void gen_bnd_jmp(DisasContext *s) static void gen_eob(DisasContext *s) { gen_update_cc_op(s); - gen_reset_hflag(s, HF_INHIBIT_IRQ_MASK); + /* If the last instruction of the previous block inhibited IRQ, + * re-enable interrupts here. The interrupt shadow never lasts + * more than one instruction, hence interrupts must always be + * re-enabled by the one-instruction tb with HF_INHIBIT_IRQ_MASK. + */ + if ((s->tb->flags & HF_INHIBIT_IRQ_MASK) !=3D 0) { + gen_reset_hflag(s, HF_INHIBIT_IRQ_MASK); + } if (s->tb->flags & HF_RF_MASK) { gen_helper_reset_rf(cpu_env); } @@ -5173,8 +5180,6 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, gen_pop_update(s, ot); if (reg =3D=3D R_SS) { /* if reg =3D=3D SS, inhibit interrupts/trace. */ - /* If several instructions disable interrupts, only the - _first_ does it */ gen_set_hflag(s, HF_INHIBIT_IRQ_MASK); s->tf =3D 0; } @@ -5240,8 +5245,6 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, gen_movl_seg_T0(s, reg); if (reg =3D=3D R_SS) { /* if reg =3D=3D SS, inhibit interrupts/trace */ - /* If several instructions disable interrupts, only the - _first_ does it */ gen_set_hflag(s, HF_INHIBIT_IRQ_MASK); s->tf =3D 0; } @@ -6778,8 +6781,6 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, gen_sti: gen_helper_sti(cpu_env); /* interruptions are enabled only the first insn after s= ti */ - /* If several instructions disable interrupts, only the - _first_ does it */ gen_set_hflag(s, HF_INHIBIT_IRQ_MASK); /* give a chance to handle pending irqs */ gen_jmp_im(s->pc - s->cs_base); --=20 2.5.0