From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57657) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aalyL-00067R-CD for qemu-devel@nongnu.org; Tue, 01 Mar 2016 10:12:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aalyF-0000Zi-7H for qemu-devel@nongnu.org; Tue, 01 Mar 2016 10:12:25 -0500 Received: from mx1.redhat.com ([209.132.183.28]:49753) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aalyE-0000ZT-W5 for qemu-devel@nongnu.org; Tue, 01 Mar 2016 10:12:19 -0500 From: Paolo Bonzini Date: Tue, 1 Mar 2016 16:12:14 +0100 Message-Id: <1456845134-18812-1-git-send-email-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH] target-i386: fix smsw and lmsw from/to register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: hpoussin@reactos.org, rth@twiddle.net SMSW and LMSW accept register operands, but commit 1906b2a ("target-i386: Rearrange processing of 0F 01", 2016-02-13) did not account for that. Fixes: 1906b2af7c2345037d9b2fdf484b457b5acd09d1 Cc: rth@twiddle.net Reported-by: Herv=C3=A9 Poussineau Signed-off-by: Paolo Bonzini --- target-i386/translate.c | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 0ed2ee9..b345e2c 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -57,11 +57,17 @@ #endif =20 /* For a switch indexed by MODRM, match all memory operands for a given = OP. */ -#define CASE_MEM_OP(OP) \ +#define CASE_MODRM_MEM_OP(OP) \ case (0 << 6) | (OP << 3) | 0 ... (0 << 6) | (OP << 3) | 7: \ case (1 << 6) | (OP << 3) | 0 ... (1 << 6) | (OP << 3) | 7: \ case (2 << 6) | (OP << 3) | 0 ... (2 << 6) | (OP << 3) | 7 =20 +#define CASE_MODRM_OP(OP) \ + case (0 << 6) | (OP << 3) | 0 ... (0 << 6) | (OP << 3) | 7: \ + case (1 << 6) | (OP << 3) | 0 ... (1 << 6) | (OP << 3) | 7: \ + case (2 << 6) | (OP << 3) | 0 ... (2 << 6) | (OP << 3) | 7: \ + case (3 << 6) | (OP << 3) | 0 ... (3 << 6) | (OP << 3) | 7 + //#define MACRO_TEST 1 =20 /* global register indexes */ @@ -7039,7 +7045,7 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, case 0x101: modrm =3D cpu_ldub_code(env, s->pc++); switch (modrm) { - CASE_MEM_OP(0): /* sgdt */ + CASE_MODRM_MEM_OP(0): /* sgdt */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ); gen_lea_modrm(env, s, modrm); tcg_gen_ld32u_tl(cpu_T0, @@ -7095,7 +7101,7 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, gen_eob(s); break; =20 - CASE_MEM_OP(1): /* sidt */ + CASE_MODRM_MEM_OP(1): /* sidt */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ); gen_lea_modrm(env, s, modrm); tcg_gen_ld32u_tl(cpu_T0, cpu_env, offsetof(CPUX86State, idt.= limit)); @@ -7241,7 +7247,7 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, gen_helper_invlpga(cpu_env, tcg_const_i32(s->aflag - 1)); break; =20 - CASE_MEM_OP(2): /* lgdt */ + CASE_MODRM_MEM_OP(2): /* lgdt */ if (s->cpl !=3D 0) { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); break; @@ -7258,7 +7264,7 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, tcg_gen_st32_tl(cpu_T1, cpu_env, offsetof(CPUX86State, gdt.l= imit)); break; =20 - CASE_MEM_OP(3): /* lidt */ + CASE_MODRM_MEM_OP(3): /* lidt */ if (s->cpl !=3D 0) { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); break; @@ -7275,7 +7281,7 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, tcg_gen_st32_tl(cpu_T1, cpu_env, offsetof(CPUX86State, idt.l= imit)); break; =20 - CASE_MEM_OP(4): /* smsw */ + CASE_MODRM_OP(4): /* smsw */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0); #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN tcg_gen_ld32u_tl(cpu_T0, cpu_env, offsetof(CPUX86State, cr[0= ]) + 4); @@ -7285,7 +7291,7 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 1); break; =20 - CASE_MEM_OP(6): /* lmsw */ + CASE_MODRM_OP(6): /* lmsw */ if (s->cpl !=3D 0) { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); break; @@ -7297,7 +7303,7 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, gen_eob(s); break; =20 - CASE_MEM_OP(7): /* invlpg */ + CASE_MODRM_MEM_OP(7): /* invlpg */ if (s->cpl !=3D 0) { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); break; @@ -7779,7 +7785,7 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, case 0x1ae: modrm =3D cpu_ldub_code(env, s->pc++); switch (modrm) { - CASE_MEM_OP(0): /* fxsave */ + CASE_MODRM_MEM_OP(0): /* fxsave */ if (!(s->cpuid_features & CPUID_FXSR) || (prefixes & PREFIX_LOCK)) { goto illegal_op; @@ -7792,7 +7798,7 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, gen_helper_fxsave(cpu_env, cpu_A0); break; =20 - CASE_MEM_OP(1): /* fxrstor */ + CASE_MODRM_MEM_OP(1): /* fxrstor */ if (!(s->cpuid_features & CPUID_FXSR) || (prefixes & PREFIX_LOCK)) { goto illegal_op; @@ -7805,7 +7811,7 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, gen_helper_fxrstor(cpu_env, cpu_A0); break; =20 - CASE_MEM_OP(2): /* ldmxcsr */ + CASE_MODRM_MEM_OP(2): /* ldmxcsr */ if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK))= { goto illegal_op; } @@ -7818,7 +7824,7 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32); break; =20 - CASE_MEM_OP(3): /* stmxcsr */ + CASE_MODRM_MEM_OP(3): /* stmxcsr */ if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK))= { goto illegal_op; } @@ -7831,7 +7837,7 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, gen_op_st_v(s, MO_32, cpu_T0, cpu_A0); break; =20 - CASE_MEM_OP(4): /* xsave */ + CASE_MODRM_MEM_OP(4): /* xsave */ if ((s->cpuid_ext_features & CPUID_EXT_XSAVE) =3D=3D 0 || (prefixes & (PREFIX_LOCK | PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) { @@ -7843,7 +7849,7 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, gen_helper_xsave(cpu_env, cpu_A0, cpu_tmp1_i64); break; =20 - CASE_MEM_OP(5): /* xrstor */ + CASE_MODRM_MEM_OP(5): /* xrstor */ if ((s->cpuid_ext_features & CPUID_EXT_XSAVE) =3D=3D 0 || (prefixes & (PREFIX_LOCK | PREFIX_DATA | PREFIX_REPZ | PREFIX_REPNZ))) { @@ -7860,7 +7866,7 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, gen_eob(s); break; =20 - CASE_MEM_OP(6): /* xsaveopt / clwb */ + CASE_MODRM_MEM_OP(6): /* xsaveopt / clwb */ if (prefixes & PREFIX_LOCK) { goto illegal_op; } @@ -7884,7 +7890,7 @@ static target_ulong disas_insn(CPUX86State *env, Di= sasContext *s, } break; =20 - CASE_MEM_OP(7): /* clflush / clflushopt */ + CASE_MODRM_MEM_OP(7): /* clflush / clflushopt */ if (prefixes & PREFIX_LOCK) { goto illegal_op; } --=20 2.5.0