From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50623) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aan6K-0004wf-Hz for qemu-devel@nongnu.org; Tue, 01 Mar 2016 11:24:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aan6F-0005NS-F5 for qemu-devel@nongnu.org; Tue, 01 Mar 2016 11:24:44 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:34250) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aan6F-0005Ll-8Y for qemu-devel@nongnu.org; Tue, 01 Mar 2016 11:24:39 -0500 From: Bastian Koppelmann Date: Tue, 1 Mar 2016 17:24:21 +0100 Message-Id: <1456849468-30217-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PATCH 0/7] TriCore FPU patches List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: rth@twiddle.net Hi, this patch-series adds the inital infrastructure for FPU instructions and adds the first few: add, sub, mul, div, cmp, ftoi, and itof. Patch [02/07] moves the general CHECK_REG_PAIR to each single instruction since add.f and sub.f do not use 64-bit registers and would generate a false exception. Cheers, Bastian Bastian Koppelmann (7): target-tricore: Add FPU infrastructure target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide target-tricore: add add.f/sub.f instructions target-tricore: Add mul.f instruction target-tricore: Add div.f instruction target-tricore: Add cmp.f instruction target-tricore: Add ftoi and itof instructions target-tricore/Makefile.objs | 2 +- target-tricore/cpu.h | 4 +- target-tricore/fpu_helper.c | 248 +++++++++++++++++++++++++++++++++++++++ target-tricore/helper.h | 7 ++ target-tricore/translate.c | 31 ++++- target-tricore/tricore-opcodes.h | 18 +++ 6 files changed, 305 insertions(+), 5 deletions(-) create mode 100644 target-tricore/fpu_helper.c -- 2.7.2