[Qemu-devel] [PATCH 0/7] TriCore FPU patches

[Qemu-devel] [PATCH 0/7] TriCore FPU patches

[Bastian Koppelmann]

Hi,

this patch-series adds the inital infrastructure for FPU instructions and adds
the first few: add, sub, mul, div, cmp, ftoi, and itof. Patch [02/07] moves
the general CHECK_REG_PAIR to each single instruction since add.f and sub.f
do not use 64-bit registers and would generate a false exception.

Cheers,
Bastian

Bastian Koppelmann (7):
  target-tricore: Add FPU infrastructure
  target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide
  target-tricore: add add.f/sub.f instructions
  target-tricore: Add mul.f instruction
  target-tricore: Add div.f instruction
  target-tricore: Add cmp.f instruction
  target-tricore: Add ftoi and itof instructions

 target-tricore/Makefile.objs     |   2 +-
 target-tricore/cpu.h             |   4 +-
 target-tricore/fpu_helper.c      | 248 +++++++++++++++++++++++++++++++++++++++
 target-tricore/helper.h          |   7 ++
 target-tricore/translate.c       |  31 ++++-
 target-tricore/tricore-opcodes.h |  18 +++
 6 files changed, 305 insertions(+), 5 deletions(-)
 create mode 100644 target-tricore/fpu_helper.c

-- 
2.7.2

[Qemu-devel] [PATCH 1/7] target-tricore: Add FPU infrastructure

[Bastian Koppelmann]

This patch adds a file for all the FPU related helpers with all the includes,
useful defines, and a function to update the status bits. Additionally it adds
a mask for the rounding mode bits of PSW as well as all the opcodes for the
FPU instructions.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/Makefile.objs     |  2 +-
 target-tricore/cpu.h             |  4 +-
 target-tricore/fpu_helper.c      | 83 ++++++++++++++++++++++++++++++++++++++++
 target-tricore/tricore-opcodes.h | 18 +++++++++
 4 files changed, 104 insertions(+), 3 deletions(-)
 create mode 100644 target-tricore/fpu_helper.c

diff --git a/target-tricore/Makefile.objs b/target-tricore/Makefile.objs
index 21e820d..7a05670 100644
--- a/target-tricore/Makefile.objs
+++ b/target-tricore/Makefile.objs
@@ -1 +1 @@
-obj-y += translate.o helper.o cpu.o op_helper.o
+obj-y += translate.o helper.o cpu.o op_helper.o fpu_helper.o
diff --git a/target-tricore/cpu.h b/target-tricore/cpu.h
index 5fee376..d85e99f 100644
--- a/target-tricore/cpu.h
+++ b/target-tricore/cpu.h
@@ -183,8 +183,7 @@ struct CPUTriCoreState {
     uint32_t M2CNT;
     uint32_t M3CNT;
     /* Floating Point Registers */
-    /* XXX: */
-
+    float_status fp_status;
     /* QEMU */
     int error_code;
     uint32_t hflags;    /* CPU State */
@@ -217,6 +216,7 @@ struct CPUTriCoreState {
 #define MASK_PSW_GW  0x00000100
 #define MASK_PSW_CDE 0x00000080
 #define MASK_PSW_CDC 0x0000007f
+#define MASK_PSW_FPU_RM 0x3000000
 
 #define MASK_SYSCON_PRO_TEN 0x2
 #define MASK_SYSCON_FCD_SF  0x1
diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c
new file mode 100644
index 0000000..ddf877e
--- /dev/null
+++ b/target-tricore/fpu_helper.c
@@ -0,0 +1,83 @@
+/*
+ *  TriCore emulation for qemu: fpu helper.
+ *
+ *  Copyright (c) 2016 Bastian Koppelmann University of Paderborn
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/helper-proto.h"
+
+#define QUIET_NAN 0x7fc00000
+#define ADD_NAN   0x7cf00001
+#define DIV_NAN   0x7fc00008
+#define MUL_NAN   0x7fc00002
+#define FPU_FS PSW_USB_C
+#define FPU_FI PSW_USB_V
+#define FPU_FV PSW_USB_SV
+#define FPU_FZ PSW_USB_AV
+#define FPU_FU PSW_USB_SAV
+
+static inline bool f_is_pos_inf(float32 arg)
+{
+    return !float32_is_neg(arg) && float32_is_infinity(arg);
+}
+
+static inline bool f_is_neg_inf(float32 arg)
+{
+    return float32_is_neg(arg) && float32_is_infinity(arg);
+}
+
+static inline bool f_is_denormal(float32 arg)
+{
+    return float32_is_zero_or_denormal(arg) && !float32_is_zero(arg);
+}
+
+static inline void f_update_psw_flags(CPUTriCoreState *env, bool calc_z)
+{
+    int8_t flags = env->fp_status.float_exception_flags;
+    int32_t some_excp = 0;
+    if (flags & float_flag_invalid) {
+        env->FPU_FI = (flags & float_flag_invalid) << 31;
+        some_excp = 1;
+    }
+    if (flags & float_flag_overflow) {
+        env->FPU_FV = 1 << 31;
+        some_excp = 1;
+    }
+    if (flags & float_flag_underflow || flags & float_flag_output_denormal) {
+        env->FPU_FU = 1 << 31;
+        some_excp = 1;
+    }
+
+    if (calc_z && (flags & float_flag_divbyzero)) {
+        env->FPU_FZ = 1 << 31;
+        some_excp = 1;
+    }
+    if (flags & float_flag_inexact || flags & float_flag_output_denormal) {
+        env->PSW |= 1 << 26;
+        some_excp = 1;
+    }
+    env->FPU_FS = some_excp;
+}
+
+static inline void f_set_flags(CPUTriCoreState *env)
+{
+    set_float_rounding_mode(env->PSW & MASK_PSW_FPU_RM, &env->fp_status);
+    set_flush_inputs_to_zero(1, &env->fp_status);
+    set_flush_to_zero(1, &env->fp_status);
+    set_float_exception_flags(0, &env->fp_status);
+}
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
index 1bfed0c..df666b0 100644
--- a/target-tricore/tricore-opcodes.h
+++ b/target-tricore/tricore-opcodes.h
@@ -1126,6 +1126,20 @@ enum {
     OPC2_32_RR_CRC32                             = 0x03,
     OPC2_32_RR_DIV                               = 0x20,
     OPC2_32_RR_DIV_U                             = 0x21,
+    OPC2_32_RR_MUL_F                             = 0x04,
+    OPC2_32_RR_DIV_F                             = 0x05,
+    OPC2_32_RR_FTOI                              = 0x10,
+    OPC2_32_RR_ITOF                              = 0x14,
+    OPC2_32_RR_CMP_F                             = 0x00,
+    OPC2_32_RR_FTOIZ                             = 0x13,
+    OPC2_32_RR_FTOQ31                            = 0x11,
+    OPC2_32_RR_FTOQ31Z                           = 0x18,
+    OPC2_32_RR_FTOU                              = 0x12,
+    OPC2_32_RR_FTOUZ                             = 0x17,
+    OPC2_32_RR_Q31TOF                            = 0x15,
+    OPC2_32_RR_QSEED_F                           = 0x19,
+    OPC2_32_RR_UPDFL                             = 0x0c,
+    OPC2_32_RR_UTOF                              = 0x16,
 };
 /* OPCM_32_RR_IDIRECT                               */
 enum {
@@ -1209,6 +1223,10 @@ enum {
     OPC2_32_RRR_IXMIN                            = 0x08,
     OPC2_32_RRR_IXMIN_U                          = 0x09,
     OPC2_32_RRR_PACK                             = 0x00,
+    OPC2_32_RRR_ADD_F                            = 0x02,
+    OPC2_32_RRR_SUB_F                            = 0x03,
+    OPC2_32_RRR_MADD_F                           = 0x06,
+    OPC2_32_RRR_MSUB_F                           = 0x07,
 };
 /*
  * RRR1 Format
-- 
2.7.2

Re: [Qemu-devel] [PATCH 1/7] target-tricore: Add FPU infrastructure

[Richard Henderson]

On 03/01/2016 08:24 AM, Bastian Koppelmann wrote:
> +static inline void f_update_psw_flags(CPUTriCoreState *env, bool calc_z)

You probably need it for compiling this intermediate patch, but probably drop
inline and let the compiler choose.  This is quite a bit of code after all...

> +{
> +    int8_t flags = env->fp_status.float_exception_flags;
> +    int32_t some_excp = 0;

You need to set float_exception_flags to zero after reading, so that you don't
re-copy the flags during the next fp insn.

> +#define FPU_FS PSW_USB_C
> +#define FPU_FI PSW_USB_V
> +#define FPU_FV PSW_USB_SV
> +#define FPU_FZ PSW_USB_AV
> +#define FPU_FU PSW_USB_SAV

What an unfortunate spec.  This is an incredibly broken way to implement fp
exception flags.

Exception flags are the sort of thing that's supposed to be collected across a
whole subroutine, without having to worry about the fp exception flags being
clobbered by the surrounding pointer arithmetic.

In order to implement proper IEEE support with this chip, one would have to
implement the fp exception word in software, clearing the PSW bits before each
group of fp instructions and storing the PSW bits after each such group.

Oh well.  You're doing what the manual says...


r~

[Qemu-devel] [PATCH 2/7] target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide

[Bastian Koppelmann]

The add.f and sub.f to be implemented don't use 64 bit registers
and a general usage of CHECK_REG_PAIR would always generate an
exception for them.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/translate.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 6d7f553..84313d2 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -7013,45 +7013,51 @@ static void decode_rrr_divide(CPUTriCoreState *env, DisasContext *ctx)
     r3 = MASK_OP_RRR_S3(ctx->opcode);
     r4 = MASK_OP_RRR_D(ctx->opcode);
 
-    CHECK_REG_PAIR(r3);
-
     switch (op2) {
     case OPC2_32_RRR_DVADJ:
+        CHECK_REG_PAIR(r3);
         CHECK_REG_PAIR(r4);
         GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
                        cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
         break;
     case OPC2_32_RRR_DVSTEP:
+        CHECK_REG_PAIR(r3);
         CHECK_REG_PAIR(r4);
         GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
                        cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
         break;
     case OPC2_32_RRR_DVSTEP_U:
+        CHECK_REG_PAIR(r3);
         CHECK_REG_PAIR(r4);
         GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
                        cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
         break;
     case OPC2_32_RRR_IXMAX:
+        CHECK_REG_PAIR(r3);
         CHECK_REG_PAIR(r4);
         GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
                        cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
         break;
     case OPC2_32_RRR_IXMAX_U:
+        CHECK_REG_PAIR(r3);
         CHECK_REG_PAIR(r4);
         GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
                        cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
         break;
     case OPC2_32_RRR_IXMIN:
+        CHECK_REG_PAIR(r3);
         CHECK_REG_PAIR(r4);
         GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
                        cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
         break;
     case OPC2_32_RRR_IXMIN_U:
+        CHECK_REG_PAIR(r3);
         CHECK_REG_PAIR(r4);
         GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
                        cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
         break;
     case OPC2_32_RRR_PACK:
+        CHECK_REG_PAIR(r3);
         gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
                         cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
         break;
-- 
2.7.2

Re: [Qemu-devel] [PATCH 2/7] target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide

[Richard Henderson]

On 03/01/2016 08:24 AM, Bastian Koppelmann wrote:
> The add.f and sub.f to be implemented don't use 64 bit registers
> and a general usage of CHECK_REG_PAIR would always generate an
> exception for them.
> 
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> ---
>  target-tricore/translate.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~

[Qemu-devel] [PATCH 3/7] target-tricore: add add.f/sub.f instructions

[Bastian Koppelmann]

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/fpu_helper.c | 31 +++++++++++++++++++++++++++++++
 target-tricore/helper.h     |  2 ++
 target-tricore/translate.c  |  6 ++++++
 3 files changed, 39 insertions(+)

diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c
index ddf877e..b840c20 100644
--- a/target-tricore/fpu_helper.c
+++ b/target-tricore/fpu_helper.c
@@ -81,3 +81,34 @@ static inline void f_set_flags(CPUTriCoreState *env)
     set_flush_to_zero(1, &env->fp_status);
     set_float_exception_flags(0, &env->fp_status);
 }
+
+#define FADD_SUB(name)                                                         \
+uint32_t helper_f##name(CPUTriCoreState *env, uint32_t r1, uint32_t r2)        \
+{                                                                              \
+    float32 arg1 = make_float32(r1);                                           \
+    float32 arg2 = make_float32(r2);                                           \
+    float32 f_result;                                                          \
+                                                                               \
+    f_set_flags(env);                                                          \
+                                                                               \
+    arg1 = float32_squash_input_denormal(arg1, &env->fp_status);               \
+    arg2 = float32_squash_input_denormal(arg2, &env->fp_status);               \
+                                                                               \
+    if (float32_is_any_nan(arg1) || float32_is_any_nan(arg2)) {                \
+        f_result = QUIET_NAN;                                                  \
+        if (float32_is_signaling_nan(arg1) ||                                  \
+            float32_is_signaling_nan(arg2)) {                                  \
+            env->fp_status.float_exception_flags |= float_flag_invalid;        \
+        }                                                                      \
+    } else if (f_is_pos_inf(arg1) && f_is_neg_inf(arg2)) {                     \
+        f_result = ADD_NAN;                                                    \
+    } else if (f_is_pos_inf(arg2) && f_is_neg_inf(arg1)) {                     \
+        f_result = ADD_NAN;                                                    \
+    } else {                                                                   \
+        f_result = float32_##name(arg1, arg2 , &env->fp_status);               \
+    }                                                                          \
+    f_update_psw_flags(env, false);                                            \
+    return (uint32_t)f_result;                                                 \
+}
+FADD_SUB(add)
+FADD_SUB(sub)
diff --git a/target-tricore/helper.h b/target-tricore/helper.h
index 2c8ed78..2f4a2bb 100644
--- a/target-tricore/helper.h
+++ b/target-tricore/helper.h
@@ -105,6 +105,8 @@ DEF_HELPER_FLAGS_1(parity, TCG_CALL_NO_RWG_SE, i32, i32)
 /* float */
 DEF_HELPER_FLAGS_4(pack, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32, i32)
 DEF_HELPER_1(unpack, i64, i32)
+DEF_HELPER_3(fadd, i32, env, i32, i32)
+DEF_HELPER_3(fsub, i32, env, i32, i32)
 /* dvinit */
 DEF_HELPER_3(dvinit_b_13, i64, env, i32, i32)
 DEF_HELPER_3(dvinit_b_131, i64, env, i32, i32)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 84313d2..04620a7 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -7061,6 +7061,12 @@ static void decode_rrr_divide(CPUTriCoreState *env, DisasContext *ctx)
         gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
                         cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
         break;
+    case OPC2_32_RRR_ADD_F:
+        gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
+        break;
+    case OPC2_32_RRR_SUB_F:
+        gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
+        break;
     default:
         generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
     }
-- 
2.7.2

Re: [Qemu-devel] [PATCH 3/7] target-tricore: add add.f/sub.f instructions

[Richard Henderson]

> +    f_set_flags(env);                                                          \

You shouldn't need to set the flags every instruction.
You ought to be able to limit the changes to reset and
stores to the PSW.

> +    arg1 = float32_squash_input_denormal(arg1, &env->fp_status);               \
> +    arg2 = float32_squash_input_denormal(arg2, &env->fp_status);               \
> +                                                                               \
> +    if (float32_is_any_nan(arg1) || float32_is_any_nan(arg2)) {                \
> +        f_result = QUIET_NAN;                                                  \
> +        if (float32_is_signaling_nan(arg1) ||                                  \
> +            float32_is_signaling_nan(arg2)) {                                  \
> +            env->fp_status.float_exception_flags |= float_flag_invalid;        \
> +        }                                                                      \
> +    } else if (f_is_pos_inf(arg1) && f_is_neg_inf(arg2)) {                     \
> +        f_result = ADD_NAN;                                                    \
> +    } else if (f_is_pos_inf(arg2) && f_is_neg_inf(arg1)) {                     \
> +        f_result = ADD_NAN;                                                    \
> +    } else {                                                                   \
> +        f_result = float32_##name(arg1, arg2 , &env->fp_status);               \
> +    }                                                                          \

If we assume that exceptional situations are, well, exceptional, then we can
re-order this to

  f_result = float32_op(arg1, arg2, &env->fp_status);
  flags = env->fp_status.float_exception_flags;
  if (flags) {
      /* If the output is a NaN, but the inputs aren't,
         we return a unique value.  */
      if ((flags & float_flag_invalid)
          && !float32_is_any_nan(arg1)
          && !float32_is_any_nan(arg2)) {
          f_result = ADD_NAN;
      }
      f_update_psw_flags(env, flags, false);
  }

This does assume that fp_status.default_nan_mode = 1, so that
float32_default_nan is returned.  Which means that first patch should touch
fpu/softfloat-specialize.h to add tricore to the list of those defaulting to
0x7fc00000.


r~

[Qemu-devel] [PATCH 4/7] target-tricore: Add mul.f instruction

[Bastian Koppelmann]

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/fpu_helper.c | 30 ++++++++++++++++++++++++++++++
 target-tricore/helper.h     |  1 +
 target-tricore/translate.c  |  3 +++
 3 files changed, 34 insertions(+)

diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c
index b840c20..70e529c 100644
--- a/target-tricore/fpu_helper.c
+++ b/target-tricore/fpu_helper.c
@@ -112,3 +112,33 @@ uint32_t helper_f##name(CPUTriCoreState *env, uint32_t r1, uint32_t r2)        \
 }
 FADD_SUB(add)
 FADD_SUB(sub)
+
+uint32_t helper_fmul(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
+{
+    float32 arg1 = make_float32(r1);
+    float32 arg2 = make_float32(r2);
+    float32 f_result;
+
+    f_set_flags(env);
+
+    arg1 = float32_squash_input_denormal(arg1, &env->fp_status);
+    arg2 = float32_squash_input_denormal(arg2, &env->fp_status);
+
+    if (float32_is_any_nan(arg1) || float32_is_any_nan(arg2)) {
+        f_result = QUIET_NAN;
+        if (float32_is_signaling_nan(arg1) || float32_is_signaling_nan(arg2)) {
+            env->fp_status.float_exception_flags |= float_flag_invalid;
+        }
+    } else if (float32_is_infinity(arg1) && float32_is_zero(arg2)) {
+        f_result = MUL_NAN;
+        env->fp_status.float_exception_flags |= float_flag_invalid;
+    } else if (float32_is_infinity(arg2) && float32_is_zero(arg1)) {
+        f_result = MUL_NAN;
+        env->fp_status.float_exception_flags |= float_flag_invalid;
+    } else {
+        f_result = float32_mul(arg1, arg2, &env->fp_status);
+    }
+    f_update_psw_flags(env, false);
+    return (uint32_t)f_result;
+
+}
diff --git a/target-tricore/helper.h b/target-tricore/helper.h
index 2f4a2bb..ac41190 100644
--- a/target-tricore/helper.h
+++ b/target-tricore/helper.h
@@ -107,6 +107,7 @@ DEF_HELPER_FLAGS_4(pack, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32, i32)
 DEF_HELPER_1(unpack, i64, i32)
 DEF_HELPER_3(fadd, i32, env, i32, i32)
 DEF_HELPER_3(fsub, i32, env, i32, i32)
+DEF_HELPER_3(fmul, i32, env, i32, i32)
 /* dvinit */
 DEF_HELPER_3(dvinit_b_13, i64, env, i32, i32)
 DEF_HELPER_3(dvinit_b_131, i64, env, i32, i32)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 04620a7..16d14f0 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -6672,6 +6672,9 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
             generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
         }
         break;
+    case OPC2_32_RR_MUL_F:
+        gen_helper_fmul(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
+        break;
     default:
         generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
     }
-- 
2.7.2

[Qemu-devel] [PATCH 5/7] target-tricore: Add div.f instruction

[Bastian Koppelmann]

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/fpu_helper.c | 29 +++++++++++++++++++++++++++++
 target-tricore/helper.h     |  1 +
 target-tricore/translate.c  |  3 +++
 3 files changed, 33 insertions(+)

diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c
index 70e529c..ee8b687 100644
--- a/target-tricore/fpu_helper.c
+++ b/target-tricore/fpu_helper.c
@@ -142,3 +142,32 @@ uint32_t helper_fmul(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
     return (uint32_t)f_result;
 
 }
+
+uint32_t helper_fdiv(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
+{
+    float32 arg1 = make_float32(r1);
+    float32 arg2 = make_float32(r2);
+    float32 f_result;
+
+    f_set_flags(env);
+
+    arg1 = float32_squash_input_denormal(arg1, &env->fp_status);
+    arg2 = float32_squash_input_denormal(arg2, &env->fp_status);
+
+    if (float32_is_any_nan(arg1) || float32_is_any_nan(arg2)) {
+        f_result = QUIET_NAN;
+        if (float32_is_signaling_nan(arg1) || float32_is_signaling_nan(arg2)) {
+            env->fp_status.float_exception_flags |= float_flag_invalid;
+        }
+    } else if (float32_is_infinity(arg1) && float32_is_infinity(arg2)) {
+        f_result = DIV_NAN;
+        env->fp_status.float_exception_flags |= float_flag_invalid;
+    } else if (float32_is_zero(arg1) && float32_is_zero(arg2)) {
+        f_result = DIV_NAN;
+        env->fp_status.float_exception_flags |= float_flag_invalid;
+    } else {
+        f_result = float32_div(arg1, arg2 , &env->fp_status);
+    }
+    f_update_psw_flags(env, true);
+    return (uint32_t)f_result;
+}
diff --git a/target-tricore/helper.h b/target-tricore/helper.h
index ac41190..f5eff36 100644
--- a/target-tricore/helper.h
+++ b/target-tricore/helper.h
@@ -108,6 +108,7 @@ DEF_HELPER_1(unpack, i64, i32)
 DEF_HELPER_3(fadd, i32, env, i32, i32)
 DEF_HELPER_3(fsub, i32, env, i32, i32)
 DEF_HELPER_3(fmul, i32, env, i32, i32)
+DEF_HELPER_3(fdiv, i32, env, i32, i32)
 /* dvinit */
 DEF_HELPER_3(dvinit_b_13, i64, env, i32, i32)
 DEF_HELPER_3(dvinit_b_131, i64, env, i32, i32)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 16d14f0..49c4969 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -6675,6 +6675,9 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
     case OPC2_32_RR_MUL_F:
         gen_helper_fmul(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
         break;
+    case OPC2_32_RR_DIV_F:
+        gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
+        break;
     default:
         generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
     }
-- 
2.7.2

[Qemu-devel] [PATCH 6/7] target-tricore: Add cmp.f instruction

[Bastian Koppelmann]

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/fpu_helper.c | 29 +++++++++++++++++++++++++++++
 target-tricore/helper.h     |  1 +
 target-tricore/translate.c  |  3 +++
 3 files changed, 33 insertions(+)

diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c
index ee8b687..ceda415 100644
--- a/target-tricore/fpu_helper.c
+++ b/target-tricore/fpu_helper.c
@@ -171,3 +171,32 @@ uint32_t helper_fdiv(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
     f_update_psw_flags(env, true);
     return (uint32_t)f_result;
 }
+
+uint32_t helper_fcmp(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
+{
+    uint32_t result = 0;
+    uint32_t lt, eq, uo;
+    float32 arg1 = make_float32(r1);
+    float32 arg2 = make_float32(r2);
+
+    set_flush_inputs_to_zero(0, &env->fp_status);
+
+    lt = float32_lt_quiet(arg1, arg2, &env->fp_status);
+    eq = float32_eq_quiet(arg1, arg2, &env->fp_status);
+    uo = float32_unordered(arg1, arg2, &env->fp_status);
+
+    result = lt;
+    result |= eq << 1;
+    result |= (!lt && !eq && !uo) << 2;
+    result |= uo << 3;
+    result |= f_is_denormal(arg1) << 4;
+    result |= f_is_denormal(arg2) << 5;
+
+    env->FPU_FS = 0;
+    if (float32_is_signaling_nan(arg1) || float32_is_signaling_nan(arg2)) {
+        env->FPU_FI = (1 << 31);
+        env->FPU_FS = 1;
+    }
+
+    return result;
+}
diff --git a/target-tricore/helper.h b/target-tricore/helper.h
index f5eff36..489530f 100644
--- a/target-tricore/helper.h
+++ b/target-tricore/helper.h
@@ -109,6 +109,7 @@ DEF_HELPER_3(fadd, i32, env, i32, i32)
 DEF_HELPER_3(fsub, i32, env, i32, i32)
 DEF_HELPER_3(fmul, i32, env, i32, i32)
 DEF_HELPER_3(fdiv, i32, env, i32, i32)
+DEF_HELPER_3(fcmp, i32, env, i32, i32)
 /* dvinit */
 DEF_HELPER_3(dvinit_b_13, i64, env, i32, i32)
 DEF_HELPER_3(dvinit_b_131, i64, env, i32, i32)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 49c4969..a6e5c64 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -6678,6 +6678,9 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
     case OPC2_32_RR_DIV_F:
         gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
         break;
+    case OPC2_32_RR_CMP_F:
+        gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
+        break;
     default:
         generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
     }
-- 
2.7.2

Re: [Qemu-devel] [PATCH 6/7] target-tricore: Add cmp.f instruction

[Richard Henderson]

On 03/01/2016 08:24 AM, Bastian Koppelmann wrote:
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> ---
>  target-tricore/fpu_helper.c | 29 +++++++++++++++++++++++++++++
>  target-tricore/helper.h     |  1 +
>  target-tricore/translate.c  |  3 +++
>  3 files changed, 33 insertions(+)
> 
> diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c
> index ee8b687..ceda415 100644
> --- a/target-tricore/fpu_helper.c
> +++ b/target-tricore/fpu_helper.c
> @@ -171,3 +171,32 @@ uint32_t helper_fdiv(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
>      f_update_psw_flags(env, true);
>      return (uint32_t)f_result;
>  }
> +
> +uint32_t helper_fcmp(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
> +{
> +    uint32_t result = 0;
> +    uint32_t lt, eq, uo;
> +    float32 arg1 = make_float32(r1);
> +    float32 arg2 = make_float32(r2);
> +
> +    set_flush_inputs_to_zero(0, &env->fp_status);
> +
> +    lt = float32_lt_quiet(arg1, arg2, &env->fp_status);
> +    eq = float32_eq_quiet(arg1, arg2, &env->fp_status);
> +    uo = float32_unordered(arg1, arg2, &env->fp_status);

Do it in one step with float32_compare.
You don't want _quiet; see below re psw_flags.

> +    env->FPU_FS = 0;
> +    if (float32_is_signaling_nan(arg1) || float32_is_signaling_nan(arg2)) {
> +        env->FPU_FI = (1 << 31);
> +        env->FPU_FS = 1;
> +    }
> +
> +    return result;

If you return flush_inputs_to_zero to 1 here, you don't have to zero it on all
other fp operations.

Why aren't you using the same f_update_psw_flags function?  The only bit that
compare can set is invalid anyway.


r~

Re: [Qemu-devel] [PATCH 6/7] target-tricore: Add cmp.f instruction

[Bastian Koppelmann]

On 03/01/2016 07:21 PM, Richard Henderson wrote:
> On 03/01/2016 08:24 AM, Bastian Koppelmann wrote:
>> +
>> +    lt = float32_lt_quiet(arg1, arg2, &env->fp_status);
>> +    eq = float32_eq_quiet(arg1, arg2, &env->fp_status);
>> +    uo = float32_unordered(arg1, arg2, &env->fp_status);
> 
> Do it in one step with float32_compare.
> You don't want _quiet; see below re psw_flags.
> 
Unfortunately, if I don't use _quiet my tests fail against real hardware...

Cheers,
Bastian

Re: [Qemu-devel] [PATCH 6/7] target-tricore: Add cmp.f instruction

[Richard Henderson]

On 03/08/2016 05:20 AM, Bastian Koppelmann wrote:
> On 03/01/2016 07:21 PM, Richard Henderson wrote:
>> On 03/01/2016 08:24 AM, Bastian Koppelmann wrote:
>>> +
>>> +    lt = float32_lt_quiet(arg1, arg2, &env->fp_status);
>>> +    eq = float32_eq_quiet(arg1, arg2, &env->fp_status);
>>> +    uo = float32_unordered(arg1, arg2, &env->fp_status);
>>
>> Do it in one step with float32_compare.
>> You don't want _quiet; see below re psw_flags.
>>
> Unfortunately, if I don't use _quiet my tests fail against real hardware...

Fail in what way?  I don't think _quiet computes all of the bits you need.


r~

Re: [Qemu-devel] [PATCH 6/7] target-tricore: Add cmp.f instruction

[Bastian Koppelmann]

On 03/08/2016 03:42 PM, Richard Henderson wrote:
> On 03/08/2016 05:20 AM, Bastian Koppelmann wrote:
>> On 03/01/2016 07:21 PM, Richard Henderson wrote:
>>> On 03/01/2016 08:24 AM, Bastian Koppelmann wrote:
>>>> +
>>>> +    lt = float32_lt_quiet(arg1, arg2, &env->fp_status);
>>>> +    eq = float32_eq_quiet(arg1, arg2, &env->fp_status);
>>>> +    uo = float32_unordered(arg1, arg2, &env->fp_status);
>>>
>>> Do it in one step with float32_compare.
>>> You don't want _quiet; see below re psw_flags.
>>>
>> Unfortunately, if I don't use _quiet my tests fail against real
>> hardware...
> 
> Fail in what way?  I don't think _quiet computes all of the bits you need.

For example, if we have arg1 = 0 and arg2 = 0xffffffff then
float32_compare will assert the invalid bit, but the hardware doesn't.

Cheers,
Bastian

Re: [Qemu-devel] [PATCH 6/7] target-tricore: Add cmp.f instruction

[Bastian Koppelmann]

On 03/08/2016 03:42 PM, Richard Henderson wrote:
> On 03/08/2016 05:20 AM, Bastian Koppelmann wrote:
>> On 03/01/2016 07:21 PM, Richard Henderson wrote:
>>> On 03/01/2016 08:24 AM, Bastian Koppelmann wrote:
>>>> +
>>>> +    lt = float32_lt_quiet(arg1, arg2, &env->fp_status);
>>>> +    eq = float32_eq_quiet(arg1, arg2, &env->fp_status);
>>>> +    uo = float32_unordered(arg1, arg2, &env->fp_status);
>>>
>>> Do it in one step with float32_compare.
>>> You don't want _quiet; see below re psw_flags.
>>>
>> Unfortunately, if I don't use _quiet my tests fail against real
>> hardware...
> 
> Fail in what way?  I don't think _quiet computes all of the bits you need.

Also as far as I see the softfloat implementation, _quiet only
determines whether an invalid exception is raised if the inputs are any
nans or just signaling nans.

Re: [Qemu-devel] [PATCH 6/7] target-tricore: Add cmp.f instruction

[Richard Henderson]

On 03/08/2016 10:11 AM, Bastian Koppelmann wrote:
> On 03/08/2016 03:42 PM, Richard Henderson wrote:
>> On 03/08/2016 05:20 AM, Bastian Koppelmann wrote:
>>> On 03/01/2016 07:21 PM, Richard Henderson wrote:
>>>> On 03/01/2016 08:24 AM, Bastian Koppelmann wrote:
>>>>> +
>>>>> +    lt = float32_lt_quiet(arg1, arg2, &env->fp_status);
>>>>> +    eq = float32_eq_quiet(arg1, arg2, &env->fp_status);
>>>>> +    uo = float32_unordered(arg1, arg2, &env->fp_status);
>>>>
>>>> Do it in one step with float32_compare.
>>>> You don't want _quiet; see below re psw_flags.
>>>>
>>> Unfortunately, if I don't use _quiet my tests fail against real
>>> hardware...
>>
>> Fail in what way?  I don't think _quiet computes all of the bits you need.
>
> Also as far as I see the softfloat implementation, _quiet only
> determines whether an invalid exception is raised if the inputs are any
> nans or just signaling nans.
>

You're right -- I mis-read the set_FI status at the bottom of the page.


r~

Re: [Qemu-devel] [PATCH 6/7] target-tricore: Add cmp.f instruction

[Bastian Koppelmann]

On 03/08/2016 04:37 PM, Richard Henderson wrote:
> On 03/08/2016 10:11 AM, Bastian Koppelmann wrote:
>> On 03/08/2016 03:42 PM, Richard Henderson wrote:
>>> On 03/08/2016 05:20 AM, Bastian Koppelmann wrote:
>>>> On 03/01/2016 07:21 PM, Richard Henderson wrote:
>>>>> On 03/01/2016 08:24 AM, Bastian Koppelmann wrote:
>>>>>> +
>>>>>> +    lt = float32_lt_quiet(arg1, arg2, &env->fp_status);
>>>>>> +    eq = float32_eq_quiet(arg1, arg2, &env->fp_status);
>>>>>> +    uo = float32_unordered(arg1, arg2, &env->fp_status);
>>>>>
>>>>> Do it in one step with float32_compare.
>>>>> You don't want _quiet; see below re psw_flags.
>>>>>
>>>> Unfortunately, if I don't use _quiet my tests fail against real
>>>> hardware...
>>>
>>> Fail in what way?  I don't think _quiet computes all of the bits you
>>> need.
>>
>> Also as far as I see the softfloat implementation, _quiet only
>> determines whether an invalid exception is raised if the inputs are any
>> nans or just signaling nans.
>>
> 
> You're right -- I mis-read the set_FI status at the bottom of the page.
> 
> 
> r~

No problem ;). I think I have a v2 ready today. Thanks again for the
great review.

Cheers,
Bastian

[Qemu-devel] [PATCH 7/7] target-tricore: Add ftoi and itof instructions

[Bastian Koppelmann]

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/fpu_helper.c | 46 +++++++++++++++++++++++++++++++++++++++++++++
 target-tricore/helper.h     |  2 ++
 target-tricore/translate.c  |  6 ++++++
 3 files changed, 54 insertions(+)

diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c
index ceda415..3c09300 100644
--- a/target-tricore/fpu_helper.c
+++ b/target-tricore/fpu_helper.c
@@ -200,3 +200,49 @@ uint32_t helper_fcmp(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
 
     return result;
 }
+
+uint32_t helper_ftoi(CPUTriCoreState *env, uint32_t arg)
+{
+    float32 f_arg = make_float32(arg);
+    int32_t result;
+
+    f_set_flags(env);
+
+    result = float32_to_int32(f_arg, &env->fp_status);
+
+    if (float32_is_any_nan(f_arg)) {
+        env->FPU_FI = (1 << 31);
+        result = 0;
+    }
+
+    env->FPU_FS = 0;
+    if (get_float_exception_flags(&env->fp_status) & float_flag_invalid) {
+        env->FPU_FI = (1 << 31);
+        env->FPU_FS = 1;
+    }
+
+    if (get_float_exception_flags(&env->fp_status) & float_flag_inexact) {
+        env->PSW |= 1 << 26;
+        env->FPU_FS = 1;
+    }
+
+    return (uint32_t)result;
+}
+
+uint32_t helper_itof(CPUTriCoreState *env, uint32_t arg)
+{
+    float32 f_result;
+
+    f_set_flags(env);
+
+    f_result = int32_to_float32(arg, &env->fp_status);
+
+    env->FPU_FS = 0;
+
+    if (get_float_exception_flags(&env->fp_status) & float_flag_inexact) {
+        env->PSW |= 1 << 26;
+        env->FPU_FS = 1;
+    }
+
+    return (uint32_t)f_result;
+}
diff --git a/target-tricore/helper.h b/target-tricore/helper.h
index 489530f..9333e16 100644
--- a/target-tricore/helper.h
+++ b/target-tricore/helper.h
@@ -110,6 +110,8 @@ DEF_HELPER_3(fsub, i32, env, i32, i32)
 DEF_HELPER_3(fmul, i32, env, i32, i32)
 DEF_HELPER_3(fdiv, i32, env, i32, i32)
 DEF_HELPER_3(fcmp, i32, env, i32, i32)
+DEF_HELPER_2(ftoi, i32, env, i32)
+DEF_HELPER_2(itof, i32, env, i32)
 /* dvinit */
 DEF_HELPER_3(dvinit_b_13, i64, env, i32, i32)
 DEF_HELPER_3(dvinit_b_131, i64, env, i32, i32)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index a6e5c64..30ff016 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -6681,6 +6681,12 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
     case OPC2_32_RR_CMP_F:
         gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
         break;
+    case OPC2_32_RR_FTOI:
+        gen_helper_ftoi(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+        break;
+    case OPC2_32_RR_ITOF:
+        gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+        break;
     default:
         generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
     }
-- 
2.7.2

Re: [Qemu-devel] [PATCH 7/7] target-tricore: Add ftoi and itof instructions

[Richard Henderson]

On 03/01/2016 08:24 AM, Bastian Koppelmann wrote:
> +    env->FPU_FS = 0;
> +    if (get_float_exception_flags(&env->fp_status) & float_flag_invalid) {
> +        env->FPU_FI = (1 << 31);
> +        env->FPU_FS = 1;
> +    }
> +
> +    if (get_float_exception_flags(&env->fp_status) & float_flag_inexact) {
> +        env->PSW |= 1 << 26;
> +        env->FPU_FS = 1;
> +    }
...
> +    env->FPU_FS = 0;
> +
> +    if (get_float_exception_flags(&env->fp_status) & float_flag_inexact) {
> +        env->PSW |= 1 << 26;
> +        env->FPU_FS = 1;
> +    }

Similar comment re f_update_psw_flags.


r~