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From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH 1/3] target-tricore: add missing break in insn decode switch stmt
Date: Tue,  1 Mar 2016 18:15:24 +0100	[thread overview]
Message-ID: <1456852526-3630-2-git-send-email-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <1456852526-3630-1-git-send-email-kbastian@mail.uni-paderborn.de>

After decoding/translating a RRR_DIVIDE type instruction we would simply
fall through and would decode/translate another unintended RRR2_MADD
instruction.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/translate.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 6d7f553..f028fb9 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -8632,6 +8632,7 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
         break;
     case OPCM_32_RRR_DIVIDE:
         decode_rrr_divide(env, ctx);
+        break;
 /* RRR2 Format */
     case OPCM_32_RRR2_MADD:
         decode_rrr2_madd(env, ctx);
-- 
2.7.2

  reply	other threads:[~2016-03-01 17:15 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-03-01 17:15 [Qemu-devel] [PATCH 0/3] TriCore bugfixes Bastian Koppelmann
2016-03-01 17:15 ` Bastian Koppelmann [this message]
2016-03-01 17:15 ` [Qemu-devel] [PATCH 2/3] target-tricore: Fix helper_msub64_q_ssov not reseting OVF bit Bastian Koppelmann
2016-03-01 17:15 ` [Qemu-devel] [PATCH 3/3] target-tricore: Fix psw_read() clearing too many bits Bastian Koppelmann

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