From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45461) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aantZ-0003C2-8f for qemu-devel@nongnu.org; Tue, 01 Mar 2016 12:15:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aantU-0007PL-EU for qemu-devel@nongnu.org; Tue, 01 Mar 2016 12:15:37 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:42741) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aantU-0007Ox-95 for qemu-devel@nongnu.org; Tue, 01 Mar 2016 12:15:32 -0500 From: Bastian Koppelmann Date: Tue, 1 Mar 2016 18:15:25 +0100 Message-Id: <1456852526-3630-3-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1456852526-3630-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1456852526-3630-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PATCH 2/3] target-tricore: Fix helper_msub64_q_ssov not reseting OVF bit List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org When this instruction does not produce an overflow the corresponding bit has to be reset. Signed-off-by: Bastian Koppelmann --- target-tricore/op_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c index 55f6724..40656c3 100644 --- a/target-tricore/op_helper.c +++ b/target-tricore/op_helper.c @@ -1045,6 +1045,8 @@ uint64_t helper_msub64_q_ssov(CPUTriCoreState *env, uint64_t r1, uint32_t r2, } else { result = INT64_MIN; } + } else { + env->PSW_USB_V = 0; } } else { if (ovf < 0) { -- 2.7.2