From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57960) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1abDF7-0002IL-Tn for qemu-devel@nongnu.org; Wed, 02 Mar 2016 15:19:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1abDF2-0005Qp-Sy for qemu-devel@nongnu.org; Wed, 02 Mar 2016 15:19:33 -0500 From: Thomas Huth Date: Wed, 2 Mar 2016 21:19:19 +0100 Message-Id: <1456949962-29920-1-git-send-email-thuth@redhat.com> Subject: [Qemu-devel] [PATCH 0/3] ppc: Define some more SPRs of POWER8 in QEMU to fix migration List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, agraf@suse.de Cc: qemu-devel@nongnu.org, kvm-ppc@vger.kernel.org While tinkering with the new kvm-unit-tests framework for Power, I discovered that a couple of SPRs are destroyed during migration. We've got to define them in QEMU and make sure that they are synchronized with the kernel to make sure that the register contents are not lost. The first patch introduces the new PSPB register from POWER8, second patcch fixes the definition of the TAR register, and the third patch (which has been taken from Ben's "Add native POWER8 platform" patch series) introduces some missing performance monitor registers. Benjamin Herrenschmidt (1): ppc: Add a few more P8 PMU SPRs Thomas Huth (2): ppc: Define the PSPB register on POWER8 ppc: Fix migration of the TAR SPR target-ppc/cpu.h | 8 ++++++++ target-ppc/translate_init.c | 45 +++++++++++++++++++++++++++++++++++++++++---- 2 files changed, 49 insertions(+), 4 deletions(-) -- 1.8.3.1