From: Andrew Jeffery <andrew@aj.id.au>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: openbmc@lists.ozlabs.org, qemu-arm <qemu-arm@nongnu.org>,
QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH v2 2/3] hw/intc: Add (new) ASPEED AST2400 AVIC device model
Date: Thu, 03 Mar 2016 15:44:29 +1030 [thread overview]
Message-ID: <1456982069.10265.11.camel@aj.id.au> (raw)
In-Reply-To: <CAFEAcA-9BBUuLdKc8--VTw8HXYE=vwZmQSFOz_eqN75n6pNdbA@mail.gmail.com>
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On Thu, 2016-02-25 at 16:29 +0000, Peter Maydell wrote:
> > + case 0x20: /* Interrupt Enable */
> > + s->int_enable |= data;
>
> Are you sure this only ORs in new 1 bits?
As in, am I sure I only want to take the newly set bits? If so, yes, as
the the following register serves to clear the field's set bits:
>
> > + break;
> > + case 0x28: /* Interrupt Enable Clear */
> > + s->int_enable &= ~data;
> > + break;
The 'int_enable', 'int_trigger' and 'edge_status' fields all use the pa
ttern of separate set and clear registers (the remaining registers may
benefit from the extract64/deposit64 helpers, I'll think about that
further). I'll add some comments to help clear this up.
Otherwise, can you rephrase the question? At face value it seems like
you're implying that I'm doing more than ORing in the new 1 bits?
Andrew
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next prev parent reply other threads:[~2016-03-03 5:14 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-16 11:34 [Qemu-devel] [PATCH v2 0/3] Add ASPEED AST2400 machine model Andrew Jeffery
2016-02-16 11:34 ` [Qemu-devel] [PATCH v2 1/3] hw/timer: Add ASPEED AST2400 timer device model Andrew Jeffery
2016-02-25 16:11 ` [Qemu-devel] [Qemu-arm] " Peter Maydell
2016-02-26 3:14 ` Andrew Jeffery
2016-02-26 10:20 ` Peter Maydell
2016-02-29 2:10 ` Andrew Jeffery
2016-02-16 11:34 ` [Qemu-devel] [PATCH v2 2/3] hw/intc: Add (new) ASPEED AST2400 AVIC " Andrew Jeffery
2016-02-25 16:29 ` [Qemu-devel] [Qemu-arm] " Peter Maydell
2016-03-02 1:09 ` Andrew Jeffery
2016-03-02 12:41 ` Peter Maydell
2016-03-03 5:14 ` Andrew Jeffery [this message]
2016-03-03 8:39 ` Peter Maydell
2016-03-03 10:16 ` Andrew Jeffery
2016-02-16 11:34 ` [Qemu-devel] [PATCH v2 3/3] hw/arm: Add ASPEED AST2400 machine type Andrew Jeffery
2016-02-25 16:36 ` [Qemu-devel] [Qemu-arm] " Peter Maydell
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