From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52207) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1abLrH-0007Oy-CF for qemu-devel@nongnu.org; Thu, 03 Mar 2016 00:31:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1abLrG-00032C-46 for qemu-devel@nongnu.org; Thu, 03 Mar 2016 00:31:31 -0500 Received: from mail-qg0-x243.google.com ([2607:f8b0:400d:c04::243]:33082) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1abLrF-000326-Vk for qemu-devel@nongnu.org; Thu, 03 Mar 2016 00:31:30 -0500 Received: by mail-qg0-x243.google.com with SMTP id y89so760985qge.0 for ; Wed, 02 Mar 2016 21:31:29 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Wed, 2 Mar 2016 21:30:47 -0800 Message-Id: <1456983051-14707-4-git-send-email-rth@twiddle.net> In-Reply-To: <1456983051-14707-1-git-send-email-rth@twiddle.net> References: <1456983051-14707-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 3/7] target-i386: Fix SMSW for 64-bit mode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, hpoussin@reactos.org In non-64-bit modes, the instruction always stores 16 bits. But in 64-bit mode, when the destination is a register, the instruction can write 32 or 64 bits. Signed-off-by: Richard Henderson --- target-i386/translate.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 10cc2fa..b73c237 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -7282,12 +7282,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, CASE_MODRM_OP(4): /* smsw */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0); -#if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN - tcg_gen_ld32u_tl(cpu_T0, cpu_env, offsetof(CPUX86State, cr[0]) + 4); -#else - tcg_gen_ld32u_tl(cpu_T0, cpu_env, offsetof(CPUX86State, cr[0])); -#endif - gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 1); + tcg_gen_ld_tl(cpu_T0, cpu_env, offsetof(CPUX86State, cr[0])); + if (CODE64(s)) { + mod = (modrm >> 6) & 3; + ot = (mod != 3 ? MO_16 : s->dflag); + } else { + ot = MO_16; + } + gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); break; CASE_MODRM_OP(6): /* lmsw */ -- 2.5.0