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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 14/30] target-arm: cpu: Move cpu_is_big_endian to header
Date: Fri,  4 Mar 2016 11:41:37 +0000	[thread overview]
Message-ID: <1457091713-10138-15-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1457091713-10138-1-git-send-email-peter.maydell@linaro.org>

From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

There is a CPU data endianness test that is used to drive the
virtio_big_endian test.

Move this up to the header so it can be more generally used for endian
tests. The KVM specific cpu_syncronize_state call is left behind in the
virtio specific function.

Rename it arm_cpu-data_is_big_endian() to more accurately capture that
this is for data accesses only.

Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/cpu.c | 19 +++----------------
 target-arm/cpu.h | 19 +++++++++++++++++++
 2 files changed, 22 insertions(+), 16 deletions(-)

diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 001fccf..352d9f8 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -369,26 +369,13 @@ static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 #endif
 }
 
-static bool arm_cpu_is_big_endian(CPUState *cs)
+static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
 {
     ARMCPU *cpu = ARM_CPU(cs);
     CPUARMState *env = &cpu->env;
-    int cur_el;
 
     cpu_synchronize_state(cs);
-
-    /* In 32bit guest endianness is determined by looking at CPSR's E bit */
-    if (!is_a64(env)) {
-        return (env->uncached_cpsr & CPSR_E) ? 1 : 0;
-    }
-
-    cur_el = arm_current_el(env);
-
-    if (cur_el == 0) {
-        return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0;
-    }
-
-    return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0;
+    return arm_cpu_data_is_big_endian(env);
 }
 
 #endif
@@ -1476,7 +1463,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
     cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
     cc->asidx_from_attrs = arm_asidx_from_attrs;
     cc->vmsd = &vmstate_arm_cpu;
-    cc->virtio_is_big_endian = arm_cpu_is_big_endian;
+    cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
     cc->write_elf64_note = arm_cpu_write_elf64_note;
     cc->write_elf32_note = arm_cpu_write_elf32_note;
 #endif
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 61b8b03..75e5ea0 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1908,6 +1908,25 @@ static inline bool arm_sctlr_b(CPUARMState *env)
         (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
 }
 
+/* Return true if the processor is in big-endian mode. */
+static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
+{
+    int cur_el;
+
+    /* In 32bit endianness is determined by looking at CPSR's E bit */
+    if (!is_a64(env)) {
+        return (env->uncached_cpsr & CPSR_E) ? 1 : 0;
+    }
+
+    cur_el = arm_current_el(env);
+
+    if (cur_el == 0) {
+        return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0;
+    }
+
+    return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0;
+}
+
 #include "exec/cpu-all.h"
 
 /* Bit usage in the TB flags field: bit 31 indicates whether we are
-- 
1.9.1

  parent reply	other threads:[~2016-03-04 11:42 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-03-04 11:41 [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 01/30] target-arm: Correct handling of writes to CPSR mode bits from gdb in usermode Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 02/30] virt: Lift the maximum RAM limit from 30GB to 255GB Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 03/30] sd.c: Handle NULL block backend in sd_get_inserted() Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 04/30] sdhci: Implement DeviceClass reset Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 05/30] hw/arm/virt: Provide a secure-only RAM if booting in Secure mode Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 06/30] loader: Add load_image_mr() to load ROM image to a MemoryRegion Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 07/30] hw/arm/virt: Load bios image to MemoryRegion, not physaddr Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 08/30] hw/arm/virt: Make first flash device Secure-only if booting secure Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 09/30] hw/arm/virt: Assume EL3 boot rom will handle PSCI if one is provided Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 10/30] bcm2835_mbox/property: replace ldl_phys/stl_phys with endian-specific accesses Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 11/30] linux-user: arm: fix coding style for some linux-user signal functions Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 12/30] linux-user: arm: pass env to get_user_code_* Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 13/30] target-arm: implement SCTLR.B, drop bswap_code Peter Maydell
2016-03-04 11:41 ` Peter Maydell [this message]
2016-03-04 11:41 ` [Qemu-devel] [PULL 15/30] arm: cpu: handle BE32 user-mode as BE Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 16/30] linux-user: arm: set CPSR.E/SCTLR.E0E correctly for BE mode Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 17/30] linux-user: arm: handle CPSR.E correctly in strex emulation Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 18/30] target-arm: implement SCTLR.EE Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 19/30] target-arm: pass DisasContext to gen_aa32_ld*/st* Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 20/30] target-arm: introduce disas flag for endianness Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 21/30] target-arm: a64: Add endianness support Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 22/30] target-arm: introduce tbflag for endianness Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 23/30] target-arm: implement setend Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 24/30] target-arm: implement BE32 mode in system emulation Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 25/30] loader: add API to load elf header Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 26/30] loader: load_elf(): Add doc comment Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 27/30] loader: Add data swap option to load-elf Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 28/30] arm: boot: Support big-endian elfs Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 29/30] hw/intc/arm_gic.c: Implement GICv2 GICC_DIR Peter Maydell
2016-03-04 11:41 ` [Qemu-devel] [PULL 30/30] target-arm: Only trap SRS from S-EL1 if specified mode is MON Peter Maydell
2016-03-04 14:05 ` [Qemu-devel] [PULL 00/30] target-arm queue Peter Maydell

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