[Qemu-devel] [PATCH v2 0/7] TriCore FPU patches

[Bastian Koppelmann <kbastian@mail.uni-paderborn.de>]

Hi,

this patch-series adds the inital infrastructure for FPU instructions and adds
the first few: add, sub, mul, div, cmp, ftoi, and itof. Patch [02/07] moves
the general CHECK_REG_PAIR to each single instruction since add.f and sub.f
do not use 64-bit registers and would generate a false exception.

Cheers,
Bastian

v1 -> v2:
    - ftoi/itof now use f_update_psw_flags to update exception flags
    - fcmp now uses float32_compare_quiet instead of doing it by hand
    - fcmp now uses f_update_psw_flags to set excp flags 
    - Make exceptional case exceptional for fadd/fsub/fmul/fdiv
    - switch arg1 and arg2 in float32_##op() since sub would otherwise
      produce false results
    - add TriCore to softfloat-specialize.h
    - add fpu_set_state() which sets fpu config on psw_write() and cpu_reset
    - add f_get_excp_flags which is used to ignore input_denormal flag

Bastian Koppelmann (7):
  target-tricore: Add FPU infrastructure
  target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide
  target-tricore: add add.f/sub.f instructions
  target-tricore: Add mul.f instruction
  target-tricore: Add div.f instruction
  target-tricore: Add cmp.f instruction
  target-tricore: Add ftoi and itof instructions

 fpu/softfloat-specialize.h       |   2 +-
 target-tricore/Makefile.objs     |   2 +-
 target-tricore/cpu.h             |   6 +-
 target-tricore/fpu_helper.c      | 226 +++++++++++++++++++++++++++++++++++++++
 target-tricore/helper.c          |  10 ++
 target-tricore/helper.h          |   7 ++
 target-tricore/translate.c       |  32 +++++-
 target-tricore/tricore-opcodes.h |  18 ++++
 8 files changed, 297 insertions(+), 6 deletions(-)
 create mode 100644 target-tricore/fpu_helper.c

-- 
2.7.2