From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52882) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1adNtE-00042K-M0 for qemu-devel@nongnu.org; Tue, 08 Mar 2016 15:06:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1adNt9-0004K2-L5 for qemu-devel@nongnu.org; Tue, 08 Mar 2016 15:05:56 -0500 From: Andrew Baumann Date: Tue, 8 Mar 2016 12:05:26 -0800 Message-ID: <1457467526-8840-6-git-send-email-Andrew.Baumann@microsoft.com> In-Reply-To: <1457467526-8840-1-git-send-email-Andrew.Baumann@microsoft.com> References: <1457467526-8840-1-git-send-email-Andrew.Baumann@microsoft.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v3 5/5] bcm2835_dma: add emulation of Raspberry Pi DMA controller List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Gr=C3=A9gory=20ESTRADE?= , Stefan Weil , Peter Crosthwaite , Andrew Baumann , qemu-arm@nongnu.org, Paolo Bonzini From: Gr=C3=A9gory ESTRADE At present, all DMA transfers complete inline (so a looping descriptor queue will lock up the device). We also do not model pause/abort, arbitrarion/priority, or debug features. Signed-off-by: Gr=C3=A9gory ESTRADE [AB: implement 2D mode, cleanup/refactoring for upstream submission] Signed-off-by: Andrew Baumann Reviewed-by: Peter Maydell --- Notes: v2: * avoid ldl_phys/stl_phys * compute address of channel structure only after asserting its validi= ty * correctly implement per-channel reset and abort bits * set channel paused bit when completing DMA hw/arm/bcm2835_peripherals.c | 26 +++ hw/dma/Makefile.objs | 1 + hw/dma/bcm2835_dma.c | 408 +++++++++++++++++++++++++++++++= ++++ include/hw/arm/bcm2835_peripherals.h | 2 + include/hw/dma/bcm2835_dma.h | 47 ++++ 5 files changed, 484 insertions(+) create mode 100644 hw/dma/bcm2835_dma.c create mode 100644 include/hw/dma/bcm2835_dma.h diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c index 4d74a18..8099a8a 100644 --- a/hw/arm/bcm2835_peripherals.c +++ b/hw/arm/bcm2835_peripherals.c @@ -88,6 +88,14 @@ static void bcm2835_peripherals_init(Object *obj) object_initialize(&s->sdhci, sizeof(s->sdhci), TYPE_SYSBUS_SDHCI); object_property_add_child(obj, "sdhci", OBJECT(&s->sdhci), NULL); qdev_set_parent_bus(DEVICE(&s->sdhci), sysbus_get_default()); + + /* DMA Channels */ + object_initialize(&s->dma, sizeof(s->dma), TYPE_BCM2835_DMA); + object_property_add_child(obj, "dma", OBJECT(&s->dma), NULL); + qdev_set_parent_bus(DEVICE(&s->dma), sysbus_get_default()); + + object_property_add_const_link(OBJECT(&s->dma), "dma-mr", + OBJECT(&s->gpu_bus_mr), &error_abort); } =20 static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) @@ -258,6 +266,24 @@ static void bcm2835_peripherals_realize(DeviceState *d= ev, Error **errp) return; } =20 + /* DMA Channels */ + object_property_set_bool(OBJECT(&s->dma), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + memory_region_add_subregion(&s->peri_mr, DMA_OFFSET, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dma), 0)); + memory_region_add_subregion(&s->peri_mr, DMA15_OFFSET, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dma), 1)); + + for (n =3D 0; n <=3D 12; n++) { + sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), n, + qdev_get_gpio_in_named(DEVICE(&s->ic), + BCM2835_IC_GPU_IRQ, + INTERRUPT_DMA0 + n)); + } } =20 static void bcm2835_peripherals_class_init(ObjectClass *oc, void *data) diff --git a/hw/dma/Makefile.objs b/hw/dma/Makefile.objs index 0e65ed0..a1abbcf 100644 --- a/hw/dma/Makefile.objs +++ b/hw/dma/Makefile.objs @@ -11,3 +11,4 @@ common-obj-$(CONFIG_SUN4M) +=3D sun4m_iommu.o =20 obj-$(CONFIG_OMAP) +=3D omap_dma.o soc_dma.o obj-$(CONFIG_PXA2XX) +=3D pxa2xx_dma.o +obj-$(CONFIG_RASPI) +=3D bcm2835_dma.o diff --git a/hw/dma/bcm2835_dma.c b/hw/dma/bcm2835_dma.c new file mode 100644 index 0000000..c7ce4e4 --- /dev/null +++ b/hw/dma/bcm2835_dma.c @@ -0,0 +1,408 @@ +/* + * Raspberry Pi emulation (c) 2012 Gregory Estrade + * This code is licensed under the GNU GPLv2 and later. + */ + +#include "qemu/osdep.h" +#include "hw/dma/bcm2835_dma.h" + +/* DMA CS Control and Status bits */ +#define BCM2708_DMA_ACTIVE (1 << 0) +#define BCM2708_DMA_END (1 << 1) /* GE */ +#define BCM2708_DMA_INT (1 << 2) +#define BCM2708_DMA_ISPAUSED (1 << 4) /* Pause requested or not active= */ +#define BCM2708_DMA_ISHELD (1 << 5) /* Is held by DREQ flow control = */ +#define BCM2708_DMA_ERR (1 << 8) +#define BCM2708_DMA_ABORT (1 << 30) /* stop current CB, go to next, = WO */ +#define BCM2708_DMA_RESET (1 << 31) /* WO, self clearing */ + +/* DMA control block "info" field bits */ +#define BCM2708_DMA_INT_EN (1 << 0) +#define BCM2708_DMA_TDMODE (1 << 1) +#define BCM2708_DMA_WAIT_RESP (1 << 3) +#define BCM2708_DMA_D_INC (1 << 4) +#define BCM2708_DMA_D_WIDTH (1 << 5) +#define BCM2708_DMA_D_DREQ (1 << 6) +#define BCM2708_DMA_D_IGNORE (1 << 7) +#define BCM2708_DMA_S_INC (1 << 8) +#define BCM2708_DMA_S_WIDTH (1 << 9) +#define BCM2708_DMA_S_DREQ (1 << 10) +#define BCM2708_DMA_S_IGNORE (1 << 11) + +/* Register offsets */ +#define BCM2708_DMA_CS 0x00 /* Control and Status */ +#define BCM2708_DMA_ADDR 0x04 /* Control block address */ +/* the current control block appears in the following registers - read onl= y */ +#define BCM2708_DMA_INFO 0x08 +#define BCM2708_DMA_SOURCE_AD 0x0c +#define BCM2708_DMA_DEST_AD 0x10 +#define BCM2708_DMA_TXFR_LEN 0x14 +#define BCM2708_DMA_STRIDE 0x18 +#define BCM2708_DMA_NEXTCB 0x1C +#define BCM2708_DMA_DEBUG 0x20 + +#define BCM2708_DMA_INT_STATUS 0xfe0 /* Interrupt status of each channel = */ +#define BCM2708_DMA_ENABLE 0xff0 /* Global enable bits for each chann= el */ + +#define BCM2708_DMA_CS_RW_MASK 0x30ff0001 /* All RW bits in DMA_CS */ + +static void bcm2835_dma_update(BCM2835DMAState *s, unsigned c) +{ + BCM2835DMAChan *ch =3D &s->chan[c]; + uint32_t data, xlen, ylen; + int16_t dst_stride, src_stride; + + if (!(s->enable & (1 << c))) { + return; + } + + while ((s->enable & (1 << c)) && (ch->conblk_ad !=3D 0)) { + /* CB fetch */ + ch->ti =3D ldl_le_phys(&s->dma_as, ch->conblk_ad); + ch->source_ad =3D ldl_le_phys(&s->dma_as, ch->conblk_ad + 4); + ch->dest_ad =3D ldl_le_phys(&s->dma_as, ch->conblk_ad + 8); + ch->txfr_len =3D ldl_le_phys(&s->dma_as, ch->conblk_ad + 12); + ch->stride =3D ldl_le_phys(&s->dma_as, ch->conblk_ad + 16); + ch->nextconbk =3D ldl_le_phys(&s->dma_as, ch->conblk_ad + 20); + + if (ch->ti & BCM2708_DMA_TDMODE) { + /* 2D transfer mode */ + ylen =3D (ch->txfr_len >> 16) & 0x3fff; + xlen =3D ch->txfr_len & 0xffff; + dst_stride =3D ch->stride >> 16; + src_stride =3D ch->stride & 0xffff; + } else { + ylen =3D 1; + xlen =3D ch->txfr_len; + dst_stride =3D 0; + src_stride =3D 0; + } + + while (ylen !=3D 0) { + /* Normal transfer mode */ + while (xlen !=3D 0) { + if (ch->ti & BCM2708_DMA_S_IGNORE) { + /* Ignore reads */ + data =3D 0; + } else { + data =3D ldl_le_phys(&s->dma_as, ch->source_ad); + } + if (ch->ti & BCM2708_DMA_S_INC) { + ch->source_ad +=3D 4; + } + + if (ch->ti & BCM2708_DMA_D_IGNORE) { + /* Ignore writes */ + } else { + stl_le_phys(&s->dma_as, ch->dest_ad, data); + } + if (ch->ti & BCM2708_DMA_D_INC) { + ch->dest_ad +=3D 4; + } + + /* update remaining transfer length */ + xlen -=3D 4; + if (ch->ti & BCM2708_DMA_TDMODE) { + ch->txfr_len =3D (ylen << 16) | xlen; + } else { + ch->txfr_len =3D xlen; + } + } + + if (--ylen !=3D 0) { + ch->source_ad +=3D src_stride; + ch->dest_ad +=3D dst_stride; + } + } + ch->cs |=3D BCM2708_DMA_END; + if (ch->ti & BCM2708_DMA_INT_EN) { + ch->cs |=3D BCM2708_DMA_INT; + s->int_status |=3D (1 << c); + qemu_set_irq(ch->irq, 1); + } + + /* Process next CB */ + ch->conblk_ad =3D ch->nextconbk; + } + + ch->cs &=3D ~BCM2708_DMA_ACTIVE; + ch->cs |=3D BCM2708_DMA_ISPAUSED; +} + +static void bcm2835_dma_chan_reset(BCM2835DMAChan *ch) +{ + ch->cs =3D 0; + ch->conblk_ad =3D 0; +} + +static uint64_t bcm2835_dma_read(BCM2835DMAState *s, hwaddr offset, + unsigned size, unsigned c) +{ + BCM2835DMAChan *ch; + uint32_t res =3D 0; + + assert(size =3D=3D 4); + assert(c < BCM2835_DMA_NCHANS); + + ch =3D &s->chan[c]; + + switch (offset) { + case BCM2708_DMA_CS: + res =3D ch->cs; + break; + case BCM2708_DMA_ADDR: + res =3D ch->conblk_ad; + break; + case BCM2708_DMA_INFO: + res =3D ch->ti; + break; + case BCM2708_DMA_SOURCE_AD: + res =3D ch->source_ad; + break; + case BCM2708_DMA_DEST_AD: + res =3D ch->dest_ad; + break; + case BCM2708_DMA_TXFR_LEN: + res =3D ch->txfr_len; + break; + case BCM2708_DMA_STRIDE: + res =3D ch->stride; + break; + case BCM2708_DMA_NEXTCB: + res =3D ch->nextconbk; + break; + case BCM2708_DMA_DEBUG: + res =3D ch->debug; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", + __func__, offset); + break; + } + return res; +} + +static void bcm2835_dma_write(BCM2835DMAState *s, hwaddr offset, + uint64_t value, unsigned size, unsigned c) +{ + BCM2835DMAChan *ch; + uint32_t oldcs; + + assert(size =3D=3D 4); + assert(c < BCM2835_DMA_NCHANS); + + ch =3D &s->chan[c]; + + switch (offset) { + case BCM2708_DMA_CS: + oldcs =3D ch->cs; + if (value & BCM2708_DMA_RESET) { + bcm2835_dma_chan_reset(ch); + } + if (value & BCM2708_DMA_ABORT) { + /* abort is a no-op, since we always run to completion */ + } + if (value & BCM2708_DMA_END) { + ch->cs &=3D ~BCM2708_DMA_END; + } + if (value & BCM2708_DMA_INT) { + ch->cs &=3D ~BCM2708_DMA_INT; + s->int_status &=3D ~(1 << c); + qemu_set_irq(ch->irq, 0); + } + ch->cs &=3D ~BCM2708_DMA_CS_RW_MASK; + ch->cs |=3D (value & BCM2708_DMA_CS_RW_MASK); + if (!(oldcs & BCM2708_DMA_ACTIVE) && (ch->cs & BCM2708_DMA_ACTIVE)= ) { + bcm2835_dma_update(s, c); + } + break; + case BCM2708_DMA_ADDR: + ch->conblk_ad =3D value; + break; + case BCM2708_DMA_DEBUG: + ch->debug =3D value; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", + __func__, offset); + break; + } +} + +static uint64_t bcm2835_dma0_read(void *opaque, hwaddr offset, unsigned si= ze) +{ + BCM2835DMAState *s =3D opaque; + + if (offset < 0xf00) { + return bcm2835_dma_read(s, (offset & 0xff), size, (offset >> 8) & = 0xf); + } else { + switch (offset) { + case BCM2708_DMA_INT_STATUS: + return s->int_status; + case BCM2708_DMA_ENABLE: + return s->enable; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\= n", + __func__, offset); + return 0; + } + } +} + +static uint64_t bcm2835_dma15_read(void *opaque, hwaddr offset, unsigned s= ize) +{ + return bcm2835_dma_read(opaque, (offset & 0xff), size, 15); +} + +static void bcm2835_dma0_write(void *opaque, hwaddr offset, uint64_t value= , + unsigned size) +{ + BCM2835DMAState *s =3D opaque; + + if (offset < 0xf00) { + bcm2835_dma_write(s, (offset & 0xff), value, size, (offset >> 8) &= 0xf); + } else { + switch (offset) { + case BCM2708_DMA_INT_STATUS: + break; + case BCM2708_DMA_ENABLE: + s->enable =3D (value & 0xffff); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\= n", + __func__, offset); + } + } + +} + +static void bcm2835_dma15_write(void *opaque, hwaddr offset, uint64_t valu= e, + unsigned size) +{ + bcm2835_dma_write(opaque, (offset & 0xff), value, size, 15); +} + +static const MemoryRegionOps bcm2835_dma0_ops =3D { + .read =3D bcm2835_dma0_read, + .write =3D bcm2835_dma0_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, +}; + +static const MemoryRegionOps bcm2835_dma15_ops =3D { + .read =3D bcm2835_dma15_read, + .write =3D bcm2835_dma15_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, +}; + +static const VMStateDescription vmstate_bcm2835_dma_chan =3D { + .name =3D TYPE_BCM2835_DMA "-chan", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(cs, BCM2835DMAChan), + VMSTATE_UINT32(conblk_ad, BCM2835DMAChan), + VMSTATE_UINT32(ti, BCM2835DMAChan), + VMSTATE_UINT32(source_ad, BCM2835DMAChan), + VMSTATE_UINT32(dest_ad, BCM2835DMAChan), + VMSTATE_UINT32(txfr_len, BCM2835DMAChan), + VMSTATE_UINT32(stride, BCM2835DMAChan), + VMSTATE_UINT32(nextconbk, BCM2835DMAChan), + VMSTATE_UINT32(debug, BCM2835DMAChan), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_bcm2835_dma =3D { + .name =3D TYPE_BCM2835_DMA, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_STRUCT_ARRAY(chan, BCM2835DMAState, BCM2835_DMA_NCHANS, 1, + vmstate_bcm2835_dma_chan, BCM2835DMAChan), + VMSTATE_UINT32(int_status, BCM2835DMAState), + VMSTATE_UINT32(enable, BCM2835DMAState), + VMSTATE_END_OF_LIST() + } +}; + +static void bcm2835_dma_init(Object *obj) +{ + BCM2835DMAState *s =3D BCM2835_DMA(obj); + int n; + + /* DMA channels 0-14 occupy a contiguous block of IO memory, along + * with the global enable and interrupt status bits. Channel 15 + * has the same register map, but is mapped at a discontiguous + * address in a separate IO block. + */ + memory_region_init_io(&s->iomem0, OBJECT(s), &bcm2835_dma0_ops, s, + TYPE_BCM2835_DMA, 0x1000); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem0); + + memory_region_init_io(&s->iomem15, OBJECT(s), &bcm2835_dma15_ops, s, + TYPE_BCM2835_DMA "-chan15", 0x100); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem15); + + for (n =3D 0; n < 16; n++) { + sysbus_init_irq(SYS_BUS_DEVICE(s), &s->chan[n].irq); + } +} + +static void bcm2835_dma_reset(DeviceState *dev) +{ + BCM2835DMAState *s =3D BCM2835_DMA(dev); + int n; + + s->enable =3D 0xffff; + s->int_status =3D 0; + for (n =3D 0; n < BCM2835_DMA_NCHANS; n++) { + bcm2835_dma_chan_reset(&s->chan[n]); + } +} + +static void bcm2835_dma_realize(DeviceState *dev, Error **errp) +{ + BCM2835DMAState *s =3D BCM2835_DMA(dev); + Error *err =3D NULL; + Object *obj; + + obj =3D object_property_get_link(OBJECT(dev), "dma-mr", &err); + if (obj =3D=3D NULL) { + error_setg(errp, "%s: required dma-mr link not found: %s", + __func__, error_get_pretty(err)); + return; + } + + s->dma_mr =3D MEMORY_REGION(obj); + address_space_init(&s->dma_as, s->dma_mr, NULL); + + bcm2835_dma_reset(dev); +} + +static void bcm2835_dma_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D bcm2835_dma_realize; + dc->reset =3D bcm2835_dma_reset; + dc->vmsd =3D &vmstate_bcm2835_dma; +} + +static TypeInfo bcm2835_dma_info =3D { + .name =3D TYPE_BCM2835_DMA, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(BCM2835DMAState), + .class_init =3D bcm2835_dma_class_init, + .instance_init =3D bcm2835_dma_init, +}; + +static void bcm2835_dma_register_types(void) +{ + type_register_static(&bcm2835_dma_info); +} + +type_init(bcm2835_dma_register_types) diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_= peripherals.h index e19d360..e12ae37 100644 --- a/include/hw/arm/bcm2835_peripherals.h +++ b/include/hw/arm/bcm2835_peripherals.h @@ -16,6 +16,7 @@ #include "hw/sysbus.h" #include "hw/char/bcm2835_aux.h" #include "hw/display/bcm2835_fb.h" +#include "hw/dma/bcm2835_dma.h" #include "hw/intc/bcm2835_ic.h" #include "hw/misc/bcm2835_property.h" #include "hw/misc/bcm2835_mbox.h" @@ -37,6 +38,7 @@ typedef struct BCM2835PeripheralState { SysBusDevice *uart0; BCM2835AuxState aux; BCM2835FBState fb; + BCM2835DMAState dma; BCM2835ICState ic; BCM2835PropertyState property; BCM2835MboxState mboxes; diff --git a/include/hw/dma/bcm2835_dma.h b/include/hw/dma/bcm2835_dma.h new file mode 100644 index 0000000..75312e2 --- /dev/null +++ b/include/hw/dma/bcm2835_dma.h @@ -0,0 +1,47 @@ +/* + * Raspberry Pi emulation (c) 2012 Gregory Estrade + * This code is licensed under the GNU GPLv2 and later. + */ + +#ifndef BCM2835_DMA_H +#define BCM2835_DMA_H + +#include "qemu-common.h" +#include "exec/address-spaces.h" +#include "hw/sysbus.h" + +typedef struct { + uint32_t cs; + uint32_t conblk_ad; + uint32_t ti; + uint32_t source_ad; + uint32_t dest_ad; + uint32_t txfr_len; + uint32_t stride; + uint32_t nextconbk; + uint32_t debug; + + qemu_irq irq; +} BCM2835DMAChan; + +#define TYPE_BCM2835_DMA "bcm2835-dma" +#define BCM2835_DMA(obj) \ + OBJECT_CHECK(BCM2835DMAState, (obj), TYPE_BCM2835_DMA) + +#define BCM2835_DMA_NCHANS 16 + +typedef struct { + /*< private >*/ + SysBusDevice busdev; + /*< public >*/ + + MemoryRegion iomem0, iomem15; + MemoryRegion *dma_mr; + AddressSpace dma_as; + + BCM2835DMAChan chan[BCM2835_DMA_NCHANS]; + uint32_t int_status; + uint32_t enable; +} BCM2835DMAState; + +#endif --=20 2.7.0