From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Cc: rth@twiddle.net
Subject: [Qemu-devel] [PATCH v3 0/7] TriCore FPU patches
Date: Wed, 9 Mar 2016 11:42:09 +0100 [thread overview]
Message-ID: <1457520136-5280-1-git-send-email-kbastian@mail.uni-paderborn.de> (raw)
Hi,
this patch-series adds the inital infrastructure for FPU instructions and adds
the first few: add, sub, mul, div, cmp, ftoi, and itof. Patch [02/07] moves
the general CHECK_REG_PAIR to each single instruction since add.f and sub.f
do not use 64-bit registers and would generate a false exception.
Cheers,
Bastian
v2 -> v3:
- substitute f_get_excp_flags() with get_float_exception_flags() for fadd/fsub/fmul/fdiv
- remove float32_squash_input_denormal() for fadd/fsub/fmul/fdiv
- remove f_get_excp_flags(), which used a magic number
- f_update_psw_flags() now computes FPU_FS conditionally
- remove double check on float_flag_invalid in f_update_psw_flags()
v1 -> v2:
- ftoi/itof now use f_update_psw_flags to update exception flags
- fcmp now uses float32_compare_quiet instead of doing it by hand
- fcmp now uses f_update_psw_flags to set excp flags
- Make exceptional case exceptional for fadd/fsub/fmul/fdiv
- switch arg1 and arg2 in float32_##op() since sub would otherwise
produce false results
- add TriCore to softfloat-specialize.h
- add fpu_set_state() which sets fpu config on psw_write() and cpu_reset
- add f_get_excp_flags which is used to ignore input_denormal flag
Bastian Koppelmann (7):
target-tricore: Add FPU infrastructure
target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide
target-tricore: add add.f/sub.f instructions
target-tricore: Add mul.f instruction
target-tricore: Add div.f instruction
target-tricore: Add cmp.f instruction
target-tricore: Add ftoi and itof instructions
fpu/softfloat-specialize.h | 2 +-
target-tricore/Makefile.objs | 2 +-
target-tricore/cpu.h | 6 +-
target-tricore/fpu_helper.c | 215 +++++++++++++++++++++++++++++++++++++++
target-tricore/helper.c | 10 ++
target-tricore/helper.h | 7 ++
target-tricore/translate.c | 32 +++++-
target-tricore/tricore-opcodes.h | 18 ++++
8 files changed, 286 insertions(+), 6 deletions(-)
create mode 100644 target-tricore/fpu_helper.c
--
2.7.2
next reply other threads:[~2016-03-09 10:42 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-09 10:42 Bastian Koppelmann [this message]
2016-03-09 10:42 ` [Qemu-devel] [PATCH v3 1/7] target-tricore: Add FPU infrastructure Bastian Koppelmann
2016-03-09 15:59 ` Richard Henderson
2016-03-09 17:30 ` Bastian Koppelmann
2016-03-09 10:42 ` [Qemu-devel] [PATCH v3 2/7] target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide Bastian Koppelmann
2016-03-09 10:42 ` [Qemu-devel] [PATCH v3 3/7] target-tricore: add add.f/sub.f instructions Bastian Koppelmann
2016-03-09 10:42 ` [Qemu-devel] [PATCH v3 4/7] target-tricore: Add mul.f instruction Bastian Koppelmann
2016-03-09 10:42 ` [Qemu-devel] [PATCH v3 5/7] target-tricore: Add div.f instruction Bastian Koppelmann
2016-03-09 10:42 ` [Qemu-devel] [PATCH v3 6/7] target-tricore: Add cmp.f instruction Bastian Koppelmann
2016-03-09 10:42 ` [Qemu-devel] [PATCH v3 7/7] target-tricore: Add ftoi and itof instructions Bastian Koppelmann
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