From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50198) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aeObA-0008BT-AL for qemu-devel@nongnu.org; Fri, 11 Mar 2016 10:03:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aeOb8-0006uN-4A for qemu-devel@nongnu.org; Fri, 11 Mar 2016 10:03:28 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:50792) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aeOb7-0006tK-TE for qemu-devel@nongnu.org; Fri, 11 Mar 2016 10:03:26 -0500 From: Bastian Koppelmann Date: Fri, 11 Mar 2016 16:03:10 +0100 Message-Id: <1457708597-3025-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PATCH v4 0/7] TriCore FPU patches List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: rth@twiddle.net Hi, this patch-series adds the inital infrastructure for FPU instructions and adds the first few: add, sub, mul, div, cmp, ftoi, and itof. Patch [02/07] moves the general CHECK_REG_PAIR to each single instruction since add.f and sub.f do not use 64-bit registers and would generate a false exception. Cheers, Bastian v3 -> v4: - re-introduce f_get_excp_flags() which explicitly states which flags to use - actually remove double check on float_flag_invalid in f_update_psw_flags() - substitute get_float_exception_flags() with f_get_excp_flags() for fadd/fsub/fmul/fdiv v2 -> v3: - substitute f_get_excp_flags() with get_float_exception_flags() for fadd/fsub/fmul/fdiv - remove float32_squash_input_denormal() for fadd/fsub/fmul/fdiv - remove f_get_excp_flags(), which used a magic number - f_update_psw_flags() now computes FPU_FS conditionally - remove double check on float_flag_invalid in f_update_psw_flags() v1 -> v2: - ftoi/itof now use f_update_psw_flags to update exception flags - fcmp now uses float32_compare_quiet instead of doing it by hand - fcmp now uses f_update_psw_flags to set excp flags - Make exceptional case exceptional for fadd/fsub/fmul/fdiv - switch arg1 and arg2 in float32_##op() since sub would otherwise produce false results - add TriCore to softfloat-specialize.h - add fpu_set_state() which sets fpu config on psw_write() and cpu_reset - add f_get_excp_flags which is used to ignore input_denormal flag Bastian Koppelmann (7): target-tricore: Add FPU infrastructure target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide target-tricore: add add.f/sub.f instructions target-tricore: Add mul.f instruction target-tricore: Add div.f instruction target-tricore: Add cmp.f instruction target-tricore: Add ftoi and itof instructions fpu/softfloat-specialize.h | 2 +- target-tricore/Makefile.objs | 2 +- target-tricore/cpu.h | 6 +- target-tricore/fpu_helper.c | 227 +++++++++++++++++++++++++++++++++++++++ target-tricore/helper.c | 10 ++ target-tricore/helper.h | 7 ++ target-tricore/translate.c | 32 +++++- target-tricore/tricore-opcodes.h | 18 ++++ 8 files changed, 298 insertions(+), 6 deletions(-) create mode 100644 target-tricore/fpu_helper.c -- 2.7.2