From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60718) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1afGKF-00077g-1J for qemu-devel@nongnu.org; Sun, 13 Mar 2016 20:25:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1afGKD-0001EC-SD for qemu-devel@nongnu.org; Sun, 13 Mar 2016 20:25:34 -0400 Received: from mail-wm0-x241.google.com ([2a00:1450:400c:c09::241]:35841) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1afGKD-0001Du-Hu for qemu-devel@nongnu.org; Sun, 13 Mar 2016 20:25:33 -0400 Received: by mail-wm0-x241.google.com with SMTP id l68so12558867wml.3 for ; Sun, 13 Mar 2016 17:25:33 -0700 (PDT) From: David Kiarie Date: Mon, 14 Mar 2016 03:24:59 +0300 Message-Id: <1457915099-11174-5-git-send-email-davidkiarie4@gmail.com> In-Reply-To: <1457915099-11174-1-git-send-email-davidkiarie4@gmail.com> References: <1457915099-11174-1-git-send-email-davidkiarie4@gmail.com> Subject: [Qemu-devel] [V7 4/4] hw/pci-host: Emulate AMD IOMMU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: marcel@redhat.com, valentine.sinitsyn@gmail.com, jan.kiszka@web.de, David Kiarie , mst@redhat.com Add AMD IOMMU emulation support to q35 chipset Signed-off-by: David Kiarie --- hw/pci-host/q35.c | 21 +++++++++++++++++++-- include/hw/i386/intel_iommu.h | 1 + 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 115fb8c..5f6298e 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -31,6 +31,7 @@ #include "hw/hw.h" #include "hw/pci-host/q35.h" #include "qapi/visitor.h" +#include "hw/i386/amd_iommu.h" /**************************************************************************** * Q35 host @@ -447,6 +448,19 @@ static void mch_init_dmar(MCHPCIState *mch) pci_setup_iommu(pci_bus, q35_host_dma_iommu, mch->iommu); } +static void mch_init_amdvi(MCHPCIState *mch) +{ + AMDIOMMUState *iommu_state; + PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(mch))); + PCIDevice *iommu; + + iommu = pci_create_simple(bus, 0x20, TYPE_AMD_IOMMU_DEVICE); + + iommu_state = AMD_IOMMU_DEVICE(iommu); + + pci_setup_iommu(bus, bridge_host_amd_iommu, iommu_state); +} + static void mch_realize(PCIDevice *d, Error **errp) { int i; @@ -505,8 +519,11 @@ static void mch_realize(PCIDevice *d, Error **errp) mch->pci_address_space, &mch->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); } - /* Intel IOMMU (VT-d) */ - if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) { + + if (object_property_get_bool(qdev_get_machine(), "iommu", NULL) && + object_property_get_bool(qdev_get_machine(), "amd-iommu", NULL)) { + mch_init_amdvi(mch); + } else if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) { mch_init_dmar(mch); } } diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 7e511e1..5a520f3 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -28,6 +28,7 @@ #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu" #define INTEL_IOMMU_DEVICE(obj) \ OBJECT_CHECK(IntelIOMMUState, (obj), TYPE_INTEL_IOMMU_DEVICE) +#define INTEL_IOMMU_STR "intel" /* DMAR Hardware Unit Definition address (IOMMU unit) */ #define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL -- 2.1.4