[Qemu-devel] [PATCH v2 00/11] hw/mips: implement Cluster Power Controller

[Leon Alrae <leon.alrae@imgtec.com>]

Here's version 2 of the patchset providing minimal CPC implementation allowing
the guest to bring up other Virtual Processors (if more than 1 are present).
Guest can check if CPC is available by reading GCR's memory-mapped registers
and put VPs into run state by writing into CPC's memory-mapped registers.

I decided to remove the depenence on outstanding GIC patchset which still
requires updating, so I cherry-picked 2 patches which introduce GCR and also
implemented a container for a CPU with VPs, GCR and CPC. Version 2 has now
the following patches:

Patch 1 implements Coherent Processing System (CPS) container which
        initializes VPs
Patches 2-4 implement GCR and add it to CPS
Patches 5-6 implement CPC and add it to CPS
Patches 7-10 minor Malta board clean-up and adding CPS to it
Patch 11 enable CMGCR bit

The container with Coherent Processing System components is enabled only if
user specifies smp > 1 on Malta board and given CPU supports CMGCR.

This series applies on top of the "default-configs: add mips-softmmu-common.mak"
patch.

Comments are welcome.

Thanks,
Leon

v2:
* save CPC's state and make use of reset function (Peter)
* CPC is disabled on reset; guest is responsible for enabling it via GCR
* remove CPC_VP_PER_CORE_MAX constant and make VP Run mask depending on num-vp
* add vp-start-running property to indicate which VPs should run from reset
* cherry-picked 2 GCR patches from GIC patch series and fixed issues
  pointed out during the review:
  1) https://lists.nongnu.org/archive/html/qemu-devel/2015-10/msg06424.html
     * moved CP0C3_CMGCR bit enabling to a separate patch (James)
  2) https://lists.nongnu.org/archive/html/qemu-devel/2015-10/msg06423.html
     * removed GIC part as GIC doesn't exist yet at that point (James)
     * mips_gcr.{c,h} files renamed to mips_cmgcr.{c,h} (James)
     * remove whitespace before ";" after MIPSGCRState definition (James)
     * changed commit message
     * replace CONFIG_MIPS_GIC with CONFIG_MIPS_CPS which is used also for
       other CPS components
     * fixed format specifiers in qemu_log_mask (use PRIx64 instead of %lx)
* create a container for CPS components as it was suggested in the GIC patch
  series (Peter)

Leon Alrae (9):
  hw/mips: implement generic MIPS Coherent Processing System container
  hw/mips/cps: create GCR block inside CPS
  hw/mips: add initial Cluster Power Controller support
  hw/mips/cps: create CPC block inside CPS
  hw/mips_malta: remove CPUMIPSState from the write_bootloader()
  hw/mips_malta: remove redundant irq and clock init
  hw/mips_malta: move CPU creation to a separate function
  hw/mips_malta: add CPS to Malta board
  target-mips: enable CM GCR in MIPS64R6-generic CPU

Yongbok Kim (2):
  target-mips: add CMGCRBase register
  hw/mips: add initial Global Config Register support

 default-configs/mips-softmmu-common.mak |   1 +
 hw/mips/Makefile.objs                   |   1 +
 hw/mips/cps.c                           | 147 ++++++++++++++++++++++++++
 hw/mips/mips_malta.c                    | 118 ++++++++++++++-------
 hw/misc/Makefile.objs                   |   2 +
 hw/misc/mips_cmgcr.c                    | 159 +++++++++++++++++++++++++++++
 hw/misc/mips_cpc.c                      | 176 ++++++++++++++++++++++++++++++++
 include/hw/mips/cps.h                   |  44 ++++++++
 include/hw/misc/mips_cmgcr.h            |  59 +++++++++++
 include/hw/misc/mips_cpc.h              |  47 +++++++++
 target-mips/cpu.h                       |   4 +-
 target-mips/translate.c                 |  28 +++++
 target-mips/translate_init.c            |   3 +-
 13 files changed, 750 insertions(+), 39 deletions(-)
 create mode 100644 hw/mips/cps.c
 create mode 100644 hw/misc/mips_cmgcr.c
 create mode 100644 hw/misc/mips_cpc.c
 create mode 100644 include/hw/mips/cps.h
 create mode 100644 include/hw/misc/mips_cmgcr.h
 create mode 100644 include/hw/misc/mips_cpc.h

-- 
2.1.0