From: Leon Alrae <leon.alrae@imgtec.com>
To: qemu-devel@nongnu.org
Cc: yongbok.kim@imgtec.com, peter.maydell@linaro.org,
james.hogan@imgtec.com, aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH v2 11/11] target-mips: enable CM GCR in MIPS64R6-generic CPU
Date: Tue, 15 Mar 2016 09:59:36 +0000 [thread overview]
Message-ID: <1458035976-23414-12-git-send-email-leon.alrae@imgtec.com> (raw)
In-Reply-To: <1458035976-23414-1-git-send-email-leon.alrae@imgtec.com>
Indicate that in the MIPS64R6-generic CPU the memory-mapped
Global Configuration Register Space is implemented.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
target-mips/translate_init.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 3192db0..b44df9e 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -663,7 +663,8 @@ static const mips_def_t mips_defs[] =
(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
(0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
.CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
+ .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
+ (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
(1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
(1 << CP0C3_RXI) | (1 << CP0C3_LPA),
.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
--
2.1.0
prev parent reply other threads:[~2016-03-15 10:00 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-15 9:59 [Qemu-devel] [PATCH v2 00/11] hw/mips: implement Cluster Power Controller Leon Alrae
2016-03-15 9:59 ` [Qemu-devel] [PATCH v2 01/11] hw/mips: implement generic MIPS Coherent Processing System container Leon Alrae
2016-03-15 9:59 ` [Qemu-devel] [PATCH v2 02/11] target-mips: add CMGCRBase register Leon Alrae
2016-03-15 9:59 ` [Qemu-devel] [PATCH v2 03/11] hw/mips: add initial Global Config Register support Leon Alrae
2016-03-15 9:59 ` [Qemu-devel] [PATCH v2 04/11] hw/mips/cps: create GCR block inside CPS Leon Alrae
2016-03-15 9:59 ` [Qemu-devel] [PATCH v2 05/11] hw/mips: add initial Cluster Power Controller support Leon Alrae
2016-03-15 9:59 ` [Qemu-devel] [PATCH v2 06/11] hw/mips/cps: create CPC block inside CPS Leon Alrae
2016-03-15 9:59 ` [Qemu-devel] [PATCH v2 07/11] hw/mips_malta: remove CPUMIPSState from the write_bootloader() Leon Alrae
2016-03-15 9:59 ` [Qemu-devel] [PATCH v2 08/11] hw/mips_malta: remove redundant irq and clock init Leon Alrae
2016-03-15 9:59 ` [Qemu-devel] [PATCH v2 09/11] hw/mips_malta: move CPU creation to a separate function Leon Alrae
2016-03-15 9:59 ` [Qemu-devel] [PATCH v2 10/11] hw/mips_malta: add CPS to Malta board Leon Alrae
2016-03-15 9:59 ` Leon Alrae [this message]
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