From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40011) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ag7zs-0006dl-9r for qemu-devel@nongnu.org; Wed, 16 Mar 2016 05:44:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ag7zo-0004ri-9h for qemu-devel@nongnu.org; Wed, 16 Mar 2016 05:44:08 -0400 From: Laurent Vivier Date: Wed, 16 Mar 2016 10:43:52 +0100 Message-Id: <1458121432-2855-1-git-send-email-lvivier@redhat.com> Subject: [Qemu-devel] [PATCH] ppc64: set MSR_SF bit List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: Laurent Vivier , dgibson@redhat.com, thuth@redhat.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org When a qemu-system-ppc64 is started, the 64-bit mode bit is not set in MSR. Signed-off-by: Laurent Vivier --- target-ppc/translate_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index bd0cffc..d7a1aeb 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -9663,7 +9663,7 @@ static void ppc_cpu_reset(CPUState *s) #if defined(TARGET_PPC64) if (env->mmu_model & POWERPC_MMU_64) { - env->msr |= (1ULL << MSR_SF); + msr |= (1ULL << MSR_SF); } #endif -- 2.5.0