From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36966) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ag8z9-00036v-4B for qemu-devel@nongnu.org; Wed, 16 Mar 2016 06:47:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ag8z8-00027V-4z for qemu-devel@nongnu.org; Wed, 16 Mar 2016 06:47:27 -0400 Received: from mail-wm0-x231.google.com ([2a00:1450:400c:c09::231]:34152) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ag8z7-00026g-KT for qemu-devel@nongnu.org; Wed, 16 Mar 2016 06:47:26 -0400 Received: by mail-wm0-x231.google.com with SMTP id p65so183589253wmp.1 for ; Wed, 16 Mar 2016 03:47:25 -0700 (PDT) Received: from 640k.lan (94-39-161-17.adsl-ull.clienti.tiscali.it. [94.39.161.17]) by smtp.gmail.com with ESMTPSA id wr2sm2418094wjc.49.2016.03.16.03.47.23 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 Mar 2016 03:47:24 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Wed, 16 Mar 2016 11:46:29 +0100 Message-Id: <1458125219-131698-20-git-send-email-pbonzini@redhat.com> In-Reply-To: <1458125219-131698-1-git-send-email-pbonzini@redhat.com> References: <1458125219-131698-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH 19/49] target-unicore32: make cpu-qom.h not target specific List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Make UniCore32CPU an opaque type within cpu-qom.h, and move all definitions of private methods, as well as all type definitions that require knowledge of the layout to cpu.h. This helps making files independent of NEED_CPU_H if they only need to pass around CPU pointers. Signed-off-by: Paolo Bonzini --- target-unicore32/cpu-qom.h | 29 +---------------------------- target-unicore32/cpu.h | 31 ++++++++++++++++++++++++++++++- 2 files changed, 31 insertions(+), 29 deletions(-) diff --git a/target-unicore32/cpu-qom.h b/target-unicore32/cpu-qom.h index e554f1f..bc68e78 100644 --- a/target-unicore32/cpu-qom.h +++ b/target-unicore32/cpu-qom.h @@ -36,33 +36,6 @@ typedef struct UniCore32CPUClass { DeviceRealize parent_realize; } UniCore32CPUClass; -/** - * UniCore32CPU: - * @env: #CPUUniCore32State - * - * A UniCore32 CPU. - */ -typedef struct UniCore32CPU { - /*< private >*/ - CPUState parent_obj; - /*< public >*/ - - CPUUniCore32State env; -} UniCore32CPU; - -static inline UniCore32CPU *uc32_env_get_cpu(CPUUniCore32State *env) -{ - return container_of(env, UniCore32CPU, env); -} - -#define ENV_GET_CPU(e) CPU(uc32_env_get_cpu(e)) - -#define ENV_OFFSET offsetof(UniCore32CPU, env) - -void uc32_cpu_do_interrupt(CPUState *cpu); -bool uc32_cpu_exec_interrupt(CPUState *cpu, int int_req); -void uc32_cpu_dump_state(CPUState *cpu, FILE *f, - fprintf_function cpu_fprintf, int flags); -hwaddr uc32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +typedef struct UniCore32CPU UniCore32CPU; #endif diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h index 9c1fbf9..22a0aef 100644 --- a/target-unicore32/cpu.h +++ b/target-unicore32/cpu.h @@ -20,6 +20,7 @@ #define CPUArchState struct CPUUniCore32State #include "qemu-common.h" +#include "cpu-qom.h" #include "exec/cpu-defs.h" #include "fpu/softfloat.h" @@ -71,6 +72,35 @@ typedef struct CPUUniCore32State { } CPUUniCore32State; +/** + * UniCore32CPU: + * @env: #CPUUniCore32State + * + * A UniCore32 CPU. + */ +struct UniCore32CPU { + /*< private >*/ + CPUState parent_obj; + /*< public >*/ + + CPUUniCore32State env; +}; + +static inline UniCore32CPU *uc32_env_get_cpu(CPUUniCore32State *env) +{ + return container_of(env, UniCore32CPU, env); +} + +#define ENV_GET_CPU(e) CPU(uc32_env_get_cpu(e)) + +#define ENV_OFFSET offsetof(UniCore32CPU, env) + +void uc32_cpu_do_interrupt(CPUState *cpu); +bool uc32_cpu_exec_interrupt(CPUState *cpu, int int_req); +void uc32_cpu_dump_state(CPUState *cpu, FILE *f, + fprintf_function cpu_fprintf, int flags); +hwaddr uc32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); + #define ASR_M (0x1f) #define ASR_MODE_USER (0x10) #define ASR_MODE_INTR (0x12) @@ -134,7 +164,6 @@ static inline int cpu_mmu_index(CPUUniCore32State *env, bool ifetch) } #include "exec/cpu-all.h" -#include "cpu-qom.h" #include "exec/exec-all.h" int uc32_cpu_exec(CPUState *s); -- 1.8.3.1