[Qemu-devel] [PATCH v2 0/3] TriCore bugfixes

[Qemu-devel] [PATCH v2 0/3] TriCore bugfixes

[Bastian Koppelmann]

Hi,

this series tackles the bugfixes found during FPU implementation
and are mostly on liners. This includes a missing break in a switch
statement, a forgotten reset of an OVF bit, and psw_read() clearing
too many bits.

Cheers,
Bastian

v1 -> v2:
    - in patch 01 another missing break was added

Bastian Koppelmann (3):
  target-tricore: add missing break in insn decode switch stmt
  target-tricore: Fix helper_msub64_q_ssov not reseting OVF bit
  target-tricore: Fix psw_read() clearing too many bits

 target-tricore/helper.c    | 2 +-
 target-tricore/op_helper.c | 2 ++
 target-tricore/translate.c | 2 ++
 3 files changed, 5 insertions(+), 1 deletion(-)

-- 
2.7.4

[Qemu-devel] [PATCH v2 1/3] target-tricore: add missing break in insn decode switch stmt

[Bastian Koppelmann]

After decoding/translating a RRR_DIVIDE/RRRR_EXTRACT_INSERT type instruction
we would simply fall through and would decode/translate another unintended
RRR2_MADD/RRRW_EXTRACT_INSERT instruction.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
v1 -> v2:
    - Add second missing break

 target-tricore/translate.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index d13e5c8..66f798a 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -8632,6 +8632,7 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
         break;
     case OPCM_32_RRR_DIVIDE:
         decode_rrr_divide(env, ctx);
+        break;
 /* RRR2 Format */
     case OPCM_32_RRR2_MADD:
         decode_rrr2_madd(env, ctx);
@@ -8661,6 +8662,7 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
 /* RRRR format */
     case OPCM_32_RRRR_EXTRACT_INSERT:
         decode_rrrr_extract_insert(env, ctx);
+        break;
 /* RRRW format */
     case OPCM_32_RRRW_EXTRACT_INSERT:
         decode_rrrw_extract_insert(env, ctx);
-- 
2.7.4

[Qemu-devel] [PATCH v2 2/3] target-tricore: Fix helper_msub64_q_ssov not reseting OVF bit

[Bastian Koppelmann]

When this instruction does not produce an overflow the corresponding
bit has to be reset.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/op_helper.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
index 55f6724..40656c3 100644
--- a/target-tricore/op_helper.c
+++ b/target-tricore/op_helper.c
@@ -1045,6 +1045,8 @@ uint64_t helper_msub64_q_ssov(CPUTriCoreState *env, uint64_t r1, uint32_t r2,
             } else {
                result = INT64_MIN;
             }
+        } else {
+            env->PSW_USB_V = 0;
         }
     } else {
         if (ovf < 0) {
-- 
2.7.4

[Qemu-devel] [PATCH v2 3/3] target-tricore: Fix psw_read() clearing too many bits

[Bastian Koppelmann]

psw_read() ought to sync the PSW value with the
cached status bits (C,V,SV,AV,SAV). For this the bits
are cleared in the PSW before they are written from the
cached bits. The clear mask is too big and clears two
additional bits.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target-tricore/helper.c b/target-tricore/helper.c
index 7d96dad..adbb6db 100644
--- a/target-tricore/helper.c
+++ b/target-tricore/helper.c
@@ -113,7 +113,7 @@ void tricore_cpu_list(FILE *f, fprintf_function cpu_fprintf)
 uint32_t psw_read(CPUTriCoreState *env)
 {
     /* clear all USB bits */
-    env->PSW &= 0xffffff;
+    env->PSW &= 0x6ffffff;
     /* now set them from the cache */
     env->PSW |= ((env->PSW_USB_C != 0) << 31);
     env->PSW |= ((env->PSW_USB_V   & (1 << 31))  >> 1);
-- 
2.7.4