From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45428) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ahzKb-00041G-VI for qemu-devel@nongnu.org; Mon, 21 Mar 2016 08:53:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ahzKb-00077P-10 for qemu-devel@nongnu.org; Mon, 21 Mar 2016 08:53:13 -0400 Received: from e06smtp07.uk.ibm.com ([195.75.94.103]:33344) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ahzKa-00076n-OU for qemu-devel@nongnu.org; Mon, 21 Mar 2016 08:53:12 -0400 Received: from localhost by e06smtp07.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Mon, 21 Mar 2016 12:53:11 -0000 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Date: Mon, 21 Mar 2016 13:52:35 +0100 Message-Id: <1458564760-31993-6-git-send-email-clg@fr.ibm.com> In-Reply-To: <1458564760-31993-1-git-send-email-clg@fr.ibm.com> References: <1458564760-31993-1-git-send-email-clg@fr.ibm.com> Subject: [Qemu-devel] [PATCH v3 05/10] ppc: Add dummy SPR_IC for POWER8 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson Cc: Thomas Huth , Cedric Le Goater , qemu-ppc@nongnu.org, qemu-devel@nongnu.org From: Benjamin Herrenschmidt It's supposed to be an instruction counter. For now make us not crash when accessing it. Signed-off-by: Benjamin Herrenschmidt Reviewed-by: Thomas Huth Reviewed-by: David Gibson --- This is required for patch "ppc: A couple more dummy POWER8 Book4 regs" target-ppc/cpu.h | 1 + target-ppc/translate_init.c | 12 ++++++++++++ 2 files changed, 13 insertions(+) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index a7da0d3e95a9..167c73f863b3 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1685,6 +1685,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch) #define SPR_MPC_MD_DBRAM1 (0x32A) #define SPR_RCPU_L2U_RA3 (0x32B) #define SPR_TAR (0x32F) +#define SPR_IC (0x350) #define SPR_VTB (0x351) #define SPR_MMCRC (0x353) #define SPR_440_INV0 (0x370) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index aaf8ad79361e..fa8d217295b9 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7924,6 +7924,17 @@ static void gen_spr_power8_pspb(CPUPPCState *env) KVM_REG_PPC_PSPB, 0); } +static void gen_spr_power8_ic(CPUPPCState *env) +{ +#if !defined(CONFIG_USER_ONLY) + spr_register_hv(env, SPR_IC, "IC", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + 0); +#endif +} + static void init_proc_book3s_64(CPUPPCState *env, int version) { gen_spr_ne_601(env); @@ -7976,6 +7987,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version) gen_spr_power8_tm(env); gen_spr_power8_pspb(env); gen_spr_vtb(env); + gen_spr_power8_ic(env); } if (version < BOOK3S_CPU_POWER8) { gen_spr_book3s_dbg(env); -- 2.1.4