From: "Cédric Le Goater" <clg@fr.ibm.com>
To: David Gibson <david@gibson.dropbear.id.au>
Cc: "Thomas Huth" <thuth@redhat.com>,
"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
qemu-devel@nongnu.org, "Alexander Graf" <agraf@suse.de>,
"Cédric Le Goater" <clg@fr.ibm.com>,
qemu-ppc@nongnu.org
Subject: [Qemu-devel] [RFC PATCH 2/2] target-ppc: fix interrupt vectors address migration
Date: Mon, 21 Mar 2016 15:02:08 +0100 [thread overview]
Message-ID: <1458568928-3055-3-git-send-email-clg@fr.ibm.com> (raw)
In-Reply-To: <1458568928-3055-1-git-send-email-clg@fr.ibm.com>
commit 2360b6e84f78 ("target-ppc: force update of msr bits in
cpu_post_load") introduced a change to restore env->excp_prefix of a
guest which could have altered its MSR_EP. To do this, cpu_post_load()
invalidates msr and then calls ppc_store_msr() with the expected value
in argument.
The problem is that ppc_store_msr() relies on a 'valid' current msr
before changing its value. The MSR_HVB and MSR_TGPR bits are excluded
from the msr reset to keep the checks valid but the MSR_IR, MSR_DR,
MSR_EP bits which are also used through the msr_{ir,dr,ep} macros, are
reseted.
This is an issue for CPUs not using MSR_EP, on the spapr platform for
instance but all book3s are impacted. If excp_prefix is restored to
some value, it will be reseted by this call, causing an ISEG exception
on spapr guests.
This patch proposal is to test the msr_mask before actually testing
the MSR_EP bit and protect excp_prefix.
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
---
Should we just move the test in cpu_post_load() and not reset MSR_EP
if it is not present in msr_mask ? like this is done for MSR_HVB and
MSR_TGPR. I think this is making assumptions on what ppc_store_msr()
is up to though.
Maybe we could add a POWERPC_FLAGS_ for this purpose ? or test the
excp_model ?
There is room for improvement in ppc_store_msr(). It might need a new
helper like ppc_restore_msr() ?
Suggestions welcomed.
target-ppc/helper_regs.h | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h
index 271fddf17f0a..2a72e000ed83 100644
--- a/target-ppc/helper_regs.h
+++ b/target-ppc/helper_regs.h
@@ -92,9 +92,11 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
/* Swap temporary saved registers with GPRs */
hreg_swap_gpr_tgpr(env);
}
- if (unlikely((value >> MSR_EP) & 1) != msr_ep) {
- /* Change the exception prefix on PowerPC 601 */
- env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000;
+ if ((env->msr_mask >> MSR_EP) & 1) {
+ if (unlikely((value >> MSR_EP) & 1) != msr_ep) {
+ /* Change the exception prefix on PowerPC 601 */
+ env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000;
+ }
}
#endif
env->msr = value;
--
2.1.4
next prev parent reply other threads:[~2016-03-21 14:11 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-21 14:02 [Qemu-devel] [RFC PATCH 0/2] ppc: fix spapr migration (TCG) Cédric Le Goater
2016-03-21 14:02 ` [Qemu-devel] [RFC PATCH 1/2] target-ppc: migrate interrupt vectors address for spapr VM Cédric Le Goater
2016-03-21 16:18 ` Thomas Huth
2016-03-21 16:45 ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
2016-03-21 16:51 ` [Qemu-devel] " Cédric Le Goater
2016-03-21 17:04 ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
2016-03-22 0:15 ` [Qemu-devel] " David Gibson
2016-03-22 7:13 ` Cédric Le Goater
2016-03-21 14:02 ` Cédric Le Goater [this message]
2016-03-22 0:19 ` [Qemu-devel] [RFC PATCH 2/2] target-ppc: fix interrupt vectors address migration David Gibson
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