From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51994) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aiMeQ-0007nA-Kp for qemu-devel@nongnu.org; Tue, 22 Mar 2016 09:47:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aiMeM-0005LM-Bn for qemu-devel@nongnu.org; Tue, 22 Mar 2016 09:47:14 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:51777) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aiMeM-0005JS-5H for qemu-devel@nongnu.org; Tue, 22 Mar 2016 09:47:10 -0400 From: Bastian Koppelmann Date: Tue, 22 Mar 2016 14:46:19 +0100 Message-Id: <1458654386-1001-4-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1458654386-1001-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1458654386-1001-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PULL 03/10] target-tricore: Fix psw_read() clearing too many bits List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org psw_read() ought to sync the PSW value with the cached status bits (C,V,SV,AV,SAV). For this the bits are cleared in the PSW before they are written from the cached bits. The clear mask is too big and clears two additional bits. Signed-off-by: Bastian Koppelmann Message-Id: <1458547383-23102-4-git-send-email-kbastian@mail.uni-paderborn.de> --- target-tricore/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-tricore/helper.c b/target-tricore/helper.c index 7d96dad..adbb6db 100644 --- a/target-tricore/helper.c +++ b/target-tricore/helper.c @@ -113,7 +113,7 @@ void tricore_cpu_list(FILE *f, fprintf_function cpu_fprintf) uint32_t psw_read(CPUTriCoreState *env) { /* clear all USB bits */ - env->PSW &= 0xffffff; + env->PSW &= 0x6ffffff; /* now set them from the cache */ env->PSW |= ((env->PSW_USB_C != 0) << 31); env->PSW |= ((env->PSW_USB_V & (1 << 31)) >> 1); -- 2.7.4