From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51982) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aiMeQ-0007n7-8m for qemu-devel@nongnu.org; Tue, 22 Mar 2016 09:47:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aiMeL-0005Kc-OW for qemu-devel@nongnu.org; Tue, 22 Mar 2016 09:47:14 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:51788) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aiMeL-0005JY-It for qemu-devel@nongnu.org; Tue, 22 Mar 2016 09:47:09 -0400 From: Bastian Koppelmann Date: Tue, 22 Mar 2016 14:46:21 +0100 Message-Id: <1458654386-1001-6-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1458654386-1001-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1458654386-1001-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PULL 05/10] target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org The add.f and sub.f to be implemented don't use 64 bit registers and a general usage of CHECK_REG_PAIR would always generate an exception for them. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Message-Id: <1457708597-3025-3-git-send-email-kbastian@mail.uni-paderborn.de> --- target-tricore/translate.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 8c429c5..bccdcc3 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -7013,45 +7013,51 @@ static void decode_rrr_divide(CPUTriCoreState *env, DisasContext *ctx) r3 = MASK_OP_RRR_S3(ctx->opcode); r4 = MASK_OP_RRR_D(ctx->opcode); - CHECK_REG_PAIR(r3); - switch (op2) { case OPC2_32_RRR_DVADJ: + CHECK_REG_PAIR(r3); CHECK_REG_PAIR(r4); GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); break; case OPC2_32_RRR_DVSTEP: + CHECK_REG_PAIR(r3); CHECK_REG_PAIR(r4); GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); break; case OPC2_32_RRR_DVSTEP_U: + CHECK_REG_PAIR(r3); CHECK_REG_PAIR(r4); GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); break; case OPC2_32_RRR_IXMAX: + CHECK_REG_PAIR(r3); CHECK_REG_PAIR(r4); GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); break; case OPC2_32_RRR_IXMAX_U: + CHECK_REG_PAIR(r3); CHECK_REG_PAIR(r4); GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); break; case OPC2_32_RRR_IXMIN: + CHECK_REG_PAIR(r3); CHECK_REG_PAIR(r4); GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); break; case OPC2_32_RRR_IXMIN_U: + CHECK_REG_PAIR(r3); CHECK_REG_PAIR(r4); GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); break; case OPC2_32_RRR_PACK: + CHECK_REG_PAIR(r3); gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); break; -- 2.7.4