From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51979) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aiMeQ-0007n6-1C for qemu-devel@nongnu.org; Tue, 22 Mar 2016 09:47:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aiMeL-0005KK-HT for qemu-devel@nongnu.org; Tue, 22 Mar 2016 09:47:13 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:51806) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aiMeL-0005K1-Bu for qemu-devel@nongnu.org; Tue, 22 Mar 2016 09:47:09 -0400 From: Bastian Koppelmann Date: Tue, 22 Mar 2016 14:46:24 +0100 Message-Id: <1458654386-1001-9-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1458654386-1001-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1458654386-1001-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PULL 08/10] target-tricore: Add div.f instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Message-Id: <1457708597-3025-6-git-send-email-kbastian@mail.uni-paderborn.de> --- target-tricore/fpu_helper.c | 26 ++++++++++++++++++++++++++ target-tricore/helper.h | 1 + target-tricore/translate.c | 3 +++ 3 files changed, 30 insertions(+) diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c index 885b1c9..eca63eb 100644 --- a/target-tricore/fpu_helper.c +++ b/target-tricore/fpu_helper.c @@ -142,3 +142,29 @@ uint32_t helper_fmul(CPUTriCoreState *env, uint32_t r1, uint32_t r2) return (uint32_t)f_result; } + +uint32_t helper_fdiv(CPUTriCoreState *env, uint32_t r1, uint32_t r2) +{ + uint32_t flags; + float32 arg1 = make_float32(r1); + float32 arg2 = make_float32(r2); + float32 f_result; + + f_result = float32_div(arg1, arg2 , &env->fp_status); + + flags = f_get_excp_flags(env); + if (flags) { + /* If the output is a NaN, but the inputs aren't, + we return a unique value. */ + if ((flags & float_flag_invalid) + && !float32_is_any_nan(arg1) + && !float32_is_any_nan(arg2)) { + f_result = DIV_NAN; + } + f_update_psw_flags(env, flags); + } else { + env->FPU_FS = 0; + } + + return (uint32_t)f_result; +} diff --git a/target-tricore/helper.h b/target-tricore/helper.h index ac41190..f5eff36 100644 --- a/target-tricore/helper.h +++ b/target-tricore/helper.h @@ -108,6 +108,7 @@ DEF_HELPER_1(unpack, i64, i32) DEF_HELPER_3(fadd, i32, env, i32, i32) DEF_HELPER_3(fsub, i32, env, i32, i32) DEF_HELPER_3(fmul, i32, env, i32, i32) +DEF_HELPER_3(fdiv, i32, env, i32, i32) /* dvinit */ DEF_HELPER_3(dvinit_b_13, i64, env, i32, i32) DEF_HELPER_3(dvinit_b_131, i64, env, i32, i32) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 3dadb17..eaa7dd5 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -6675,6 +6675,9 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) case OPC2_32_RR_MUL_F: gen_helper_fmul(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); break; + case OPC2_32_RR_DIV_F: + gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); + break; default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } -- 2.7.4