From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33155) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aiN8F-0005OF-6P for qemu-devel@nongnu.org; Tue, 22 Mar 2016 10:18:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aiN88-0006m1-VT for qemu-devel@nongnu.org; Tue, 22 Mar 2016 10:18:03 -0400 Received: from mx1.redhat.com ([209.132.183.28]:37127) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aiN88-0006lx-O2 for qemu-devel@nongnu.org; Tue, 22 Mar 2016 10:17:56 -0400 From: Paolo Bonzini Date: Tue, 22 Mar 2016 15:17:04 +0100 Message-Id: <1458656229-32043-25-git-send-email-pbonzini@redhat.com> In-Reply-To: <1458656229-32043-1-git-send-email-pbonzini@redhat.com> References: <1458656229-32043-1-git-send-email-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 24/29] cputlb: modernise the debug support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= From: Alex Benn=C3=A9e To avoid cluttering the code with #ifdef legs we wrap up the print statements into a tlb_debug() macro. As access to the virtual TLB can get quite heavy defining DEBUG_TLB_LOG will ensure all the logs go to the qemu_log target of CPU_LOG_MMU instead of stderr. This remains compile time optional as these debug statements haven't been considered for usefulness for user visible logging. I've also removed DEBUG_TLB_CHECK which wasn't used. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-Id: <1458052224-9316-11-git-send-email-alex.bennee@linaro.org> Signed-off-by: Paolo Bonzini --- cputlb.c | 88 ++++++++++++++++++++++++++++++++--------------------------= ------ 1 file changed, 44 insertions(+), 44 deletions(-) diff --git a/cputlb.c b/cputlb.c index 2f7a166..466663b 100644 --- a/cputlb.c +++ b/cputlb.c @@ -30,8 +30,30 @@ #include "exec/ram_addr.h" #include "tcg/tcg.h" =20 -//#define DEBUG_TLB -//#define DEBUG_TLB_CHECK +/* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target = */ +/* #define DEBUG_TLB */ +/* #define DEBUG_TLB_LOG */ + +#ifdef DEBUG_TLB +# define DEBUG_TLB_GATE 1 +# ifdef DEBUG_TLB_LOG +# define DEBUG_TLB_LOG_GATE 1 +# else +# define DEBUG_TLB_LOG_GATE 0 +# endif +#else +# define DEBUG_TLB_GATE 0 +# define DEBUG_TLB_LOG_GATE 0 +#endif + +#define tlb_debug(fmt, ...) do { \ + if (DEBUG_TLB_LOG_GATE) { \ + qemu_log_mask(CPU_LOG_MMU, "%s: " fmt, __func__, \ + ## __VA_ARGS__); \ + } else if (DEBUG_TLB_GATE) { \ + fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \ + } \ +} while (0) =20 /* statistics */ int tlb_flush_count; @@ -52,9 +74,8 @@ void tlb_flush(CPUState *cpu, int flush_global) { CPUArchState *env =3D cpu->env_ptr; =20 -#if defined(DEBUG_TLB) - printf("tlb_flush:\n"); -#endif + tlb_debug("(%d)\n", flush_global); + /* must reset current TB so that interrupts cannot modify the links while we are modifying them */ cpu->current_tb =3D NULL; @@ -73,9 +94,7 @@ static inline void v_tlb_flush_by_mmuidx(CPUState *cpu,= va_list argp) { CPUArchState *env =3D cpu->env_ptr; =20 -#if defined(DEBUG_TLB) - printf("tlb_flush_by_mmuidx:"); -#endif + tlb_debug("start\n"); /* must reset current TB so that interrupts cannot modify the links while we are modifying them */ cpu->current_tb =3D NULL; @@ -87,18 +106,12 @@ static inline void v_tlb_flush_by_mmuidx(CPUState *c= pu, va_list argp) break; } =20 -#if defined(DEBUG_TLB) - printf(" %d", mmu_idx); -#endif + tlb_debug("%d\n", mmu_idx); =20 memset(env->tlb_table[mmu_idx], -1, sizeof(env->tlb_table[0])); memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[0]= )); } =20 -#if defined(DEBUG_TLB) - printf("\n"); -#endif - memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache)); } =20 @@ -128,16 +141,14 @@ void tlb_flush_page(CPUState *cpu, target_ulong add= r) int i; int mmu_idx; =20 -#if defined(DEBUG_TLB) - printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr); -#endif + tlb_debug("page :" TARGET_FMT_lx "\n", addr); + /* Check if we need to flush due to large pages. */ if ((addr & env->tlb_flush_mask) =3D=3D env->tlb_flush_addr) { -#if defined(DEBUG_TLB) - printf("tlb_flush_page: forced full flush (" - TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", - env->tlb_flush_addr, env->tlb_flush_mask); -#endif + tlb_debug("forcing full flush (" + TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", + env->tlb_flush_addr, env->tlb_flush_mask); + tlb_flush(cpu, 1); return; } @@ -170,16 +181,14 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target= _ulong addr, ...) =20 va_start(argp, addr); =20 -#if defined(DEBUG_TLB) - printf("tlb_flush_page_by_mmu_idx: " TARGET_FMT_lx, addr); -#endif + tlb_debug("addr "TARGET_FMT_lx"\n", addr); + /* Check if we need to flush due to large pages. */ if ((addr & env->tlb_flush_mask) =3D=3D env->tlb_flush_addr) { -#if defined(DEBUG_TLB) - printf(" forced full flush (" - TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", - env->tlb_flush_addr, env->tlb_flush_mask); -#endif + tlb_debug("forced full flush (" + TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", + env->tlb_flush_addr, env->tlb_flush_mask); + v_tlb_flush_by_mmuidx(cpu, argp); va_end(argp); return; @@ -198,9 +207,7 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_u= long addr, ...) break; } =20 -#if defined(DEBUG_TLB) - printf(" %d", mmu_idx); -#endif + tlb_debug("idx %d\n", mmu_idx); =20 tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr); =20 @@ -211,10 +218,6 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_= ulong addr, ...) } va_end(argp); =20 -#if defined(DEBUG_TLB) - printf("\n"); -#endif - tb_flush_jmp_cache(cpu, addr); } =20 @@ -367,12 +370,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_u= long vaddr, section =3D address_space_translate_for_iotlb(cpu, asidx, paddr, &xl= at, &sz); assert(sz >=3D TARGET_PAGE_SIZE); =20 -#if defined(DEBUG_TLB) - qemu_log_mask(CPU_LOG_MMU, - "tlb_set_page: vaddr=3D" TARGET_FMT_lx " paddr=3D0x" TARGET_F= MT_plx - " prot=3D%x idx=3D%d\n", - vaddr, paddr, prot, mmu_idx); -#endif + tlb_debug("vaddr=3D" TARGET_FMT_lx " paddr=3D0x" TARGET_FMT_plx + " prot=3D%x idx=3D%d\n", + vaddr, paddr, prot, mmu_idx); =20 address =3D vaddr; if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(sec= tion->mr)) { --=20 2.5.0