From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: Laurent Vivier <lvivier@redhat.com>,
thuth@redhat.com, agraf@suse.de, qemu-devel@nongnu.org,
clg@fr.ibm.com, qemu-ppc@nongnu.org,
David Gibson <david@gibson.dropbear.id.au>
Subject: [Qemu-devel] [PULL 01/16] ppc64: set MSR_SF bit
Date: Thu, 24 Mar 2016 15:30:43 +1100 [thread overview]
Message-ID: <1458793858-4010-2-git-send-email-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <1458793858-4010-1-git-send-email-david@gibson.dropbear.id.au>
From: Laurent Vivier <lvivier@redhat.com>
When a qemu-system-ppc64 is started, the 64-bit mode bit
is not set in MSR.
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/translate_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index fb206af..11d5fd3 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -9703,7 +9703,7 @@ static void ppc_cpu_reset(CPUState *s)
#if defined(TARGET_PPC64)
if (env->mmu_model & POWERPC_MMU_64) {
- env->msr |= (1ULL << MSR_SF);
+ msr |= (1ULL << MSR_SF);
}
#endif
--
2.5.5
next prev parent reply other threads:[~2016-03-24 4:30 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-24 4:30 [Qemu-devel] [PULL 00/16] ppc-for-2.6 queue 20160324 David Gibson
2016-03-24 4:30 ` David Gibson [this message]
2016-03-24 4:30 ` [Qemu-devel] [PULL 02/16] spapr/target-ppc/kvm: Only add hcall-instructions if KVM supports it David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 03/16] ppc: Update SPR definitions David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 04/16] ppc: Add macros to register hypervisor mode SPRs David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 05/16] ppc: Add a bunch of hypervisor SPRs to Book3s David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 06/16] ppc: Create cpu_ppc_set_papr() helper David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 07/16] ppc: Add dummy SPR_IC for POWER8 David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 08/16] ppc: Initialize AMOR in PAPR mode David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 09/16] ppc: Fix writing to AMR/UAMOR David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 10/16] ppc: Add POWER8 IAMR register David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 11/16] ppc: Add dummy CIABR SPR David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 12/16] ppc: A couple more dummy POWER8 Book4 regs David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 13/16] hw/net/spapr_llan: Extract rx buffer code into separate functions David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 14/16] hw/net/spapr_llan: Fix receive buffer handling for better performance David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 15/16] hw/net/spapr_llan: Enable the RX buffer pools by default for new machines David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 16/16] ppc: move POWER8 Book4 regs in their own routine David Gibson
2016-03-24 15:59 ` [Qemu-devel] [PULL 00/16] ppc-for-2.6 queue 20160324 Peter Maydell
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