From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: thuth@redhat.com, agraf@suse.de, qemu-devel@nongnu.org,
clg@fr.ibm.com, qemu-ppc@nongnu.org,
David Gibson <david@gibson.dropbear.id.au>
Subject: [Qemu-devel] [PULL 04/16] ppc: Add macros to register hypervisor mode SPRs
Date: Thu, 24 Mar 2016 15:30:46 +1100 [thread overview]
Message-ID: <1458793858-4010-5-git-send-email-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <1458793858-4010-1-git-send-email-david@gibson.dropbear.id.au>
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
The current set of spr_register_* macros only take the user and
supervisor function pointers. To make the transition easy, we
don't change that but we add "_hv" variants that can be used to
register all 3 sets.
To simplify the transition, users of the "old" macro will set the
hypervisor callback to be the same as the supervisor one. The new
registration function only needs to be used for registers that are
either hypervisor only or behave differently in HV mode.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
[clg: fixed else if condition in gen_op_mfspr() ]
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target-ppc/translate.c | 26 ++++++++++++++++----------
target-ppc/translate_init.c | 35 +++++++++++++++++++++++++++++++----
2 files changed, 47 insertions(+), 14 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index e402ff9..6f0e7b4 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -4282,14 +4282,17 @@ static inline void gen_op_mfspr(DisasContext *ctx)
void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
uint32_t sprn = SPR(ctx->opcode);
-#if !defined(CONFIG_USER_ONLY)
- if (ctx->hv)
+#if defined(CONFIG_USER_ONLY)
+ read_cb = ctx->spr_cb[sprn].uea_read;
+#else
+ if (ctx->pr) {
+ read_cb = ctx->spr_cb[sprn].uea_read;
+ } else if (ctx->hv) {
read_cb = ctx->spr_cb[sprn].hea_read;
- else if (!ctx->pr)
+ } else {
read_cb = ctx->spr_cb[sprn].oea_read;
- else
+ }
#endif
- read_cb = ctx->spr_cb[sprn].uea_read;
if (likely(read_cb != NULL)) {
if (likely(read_cb != SPR_NOACCESS)) {
(*read_cb)(ctx, rD(ctx->opcode), sprn);
@@ -4437,14 +4440,17 @@ static void gen_mtspr(DisasContext *ctx)
void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
uint32_t sprn = SPR(ctx->opcode);
-#if !defined(CONFIG_USER_ONLY)
- if (ctx->hv)
+#if defined(CONFIG_USER_ONLY)
+ write_cb = ctx->spr_cb[sprn].uea_write;
+#else
+ if (ctx->pr) {
+ write_cb = ctx->spr_cb[sprn].uea_write;
+ } else if (ctx->hv) {
write_cb = ctx->spr_cb[sprn].hea_write;
- else if (!ctx->pr)
+ } else {
write_cb = ctx->spr_cb[sprn].oea_write;
- else
+ }
#endif
- write_cb = ctx->spr_cb[sprn].uea_write;
if (likely(write_cb != NULL)) {
if (likely(write_cb != SPR_NOACCESS)) {
(*write_cb)(ctx, sprn, rS(ctx->opcode));
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 11d5fd3..ebfce5d 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -579,17 +579,33 @@ static inline void vscr_init (CPUPPCState *env, uint32_t val)
#define spr_register_kvm(env, num, name, uea_read, uea_write, \
oea_read, oea_write, one_reg_id, initial_value) \
_spr_register(env, num, name, uea_read, uea_write, initial_value)
+#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, hea_read, hea_write, \
+ one_reg_id, initial_value) \
+ _spr_register(env, num, name, uea_read, uea_write, initial_value)
#else
#if !defined(CONFIG_KVM)
#define spr_register_kvm(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, one_reg_id, initial_value) \
+ oea_read, oea_write, one_reg_id, initial_value) \
+ _spr_register(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, oea_read, oea_write, initial_value)
+#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, hea_read, hea_write, \
+ one_reg_id, initial_value) \
_spr_register(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, initial_value)
+ oea_read, oea_write, hea_read, hea_write, initial_value)
#else
#define spr_register_kvm(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, one_reg_id, initial_value) \
+ oea_read, oea_write, one_reg_id, initial_value) \
+ _spr_register(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, oea_read, oea_write, \
+ one_reg_id, initial_value)
+#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, hea_read, hea_write, \
+ one_reg_id, initial_value) \
_spr_register(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, one_reg_id, initial_value)
+ oea_read, oea_write, hea_read, hea_write, \
+ one_reg_id, initial_value)
#endif
#endif
@@ -598,6 +614,13 @@ static inline void vscr_init (CPUPPCState *env, uint32_t val)
spr_register_kvm(env, num, name, uea_read, uea_write, \
oea_read, oea_write, 0, initial_value)
+#define spr_register_hv(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, hea_read, hea_write, \
+ initial_value) \
+ spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, hea_read, hea_write, \
+ 0, initial_value)
+
static inline void _spr_register(CPUPPCState *env, int num,
const char *name,
void (*uea_read)(DisasContext *ctx, int gprn, int sprn),
@@ -606,6 +629,8 @@ static inline void _spr_register(CPUPPCState *env, int num,
void (*oea_read)(DisasContext *ctx, int gprn, int sprn),
void (*oea_write)(DisasContext *ctx, int sprn, int gprn),
+ void (*hea_read)(DisasContext *opaque, int gprn, int sprn),
+ void (*hea_write)(DisasContext *opaque, int sprn, int gprn),
#endif
#if defined(CONFIG_KVM)
uint64_t one_reg_id,
@@ -633,6 +658,8 @@ static inline void _spr_register(CPUPPCState *env, int num,
#if !defined(CONFIG_USER_ONLY)
spr->oea_read = oea_read;
spr->oea_write = oea_write;
+ spr->hea_read = hea_read;
+ spr->hea_write = hea_write;
#endif
#if defined(CONFIG_KVM)
spr->one_reg_id = one_reg_id,
--
2.5.5
next prev parent reply other threads:[~2016-03-24 4:30 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-24 4:30 [Qemu-devel] [PULL 00/16] ppc-for-2.6 queue 20160324 David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 01/16] ppc64: set MSR_SF bit David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 02/16] spapr/target-ppc/kvm: Only add hcall-instructions if KVM supports it David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 03/16] ppc: Update SPR definitions David Gibson
2016-03-24 4:30 ` David Gibson [this message]
2016-03-24 4:30 ` [Qemu-devel] [PULL 05/16] ppc: Add a bunch of hypervisor SPRs to Book3s David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 06/16] ppc: Create cpu_ppc_set_papr() helper David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 07/16] ppc: Add dummy SPR_IC for POWER8 David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 08/16] ppc: Initialize AMOR in PAPR mode David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 09/16] ppc: Fix writing to AMR/UAMOR David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 10/16] ppc: Add POWER8 IAMR register David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 11/16] ppc: Add dummy CIABR SPR David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 12/16] ppc: A couple more dummy POWER8 Book4 regs David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 13/16] hw/net/spapr_llan: Extract rx buffer code into separate functions David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 14/16] hw/net/spapr_llan: Fix receive buffer handling for better performance David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 15/16] hw/net/spapr_llan: Enable the RX buffer pools by default for new machines David Gibson
2016-03-24 4:30 ` [Qemu-devel] [PULL 16/16] ppc: move POWER8 Book4 regs in their own routine David Gibson
2016-03-24 15:59 ` [Qemu-devel] [PULL 00/16] ppc-for-2.6 queue 20160324 Peter Maydell
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